Electronic Design
Collaborative Effort Augments Smart Terabit System Processing

Collaborative Effort Augments Smart Terabit System Processing

MoSys and EZchip Semiconductor combined their strengths to create a solution that delivers new levels of flexibility, scalability, and performance for smart and secure terabit routers, switches, and network appliances used in carrier, cloud, and data-center networks. Revealed at DesignCon, MoSys’ Bandwidth Engine 3 family was optimized specifically for EZchip’s NPS family of C-programmable network processors. The 400-Gb/s NPS family includes features such as 256 C-programmable processors, 4K threads, traffic management, deep packet inspection, and search accelerations. The Bandwidth Engine 3 architecture offers low pin count, serial memory interface, 1-Gb of high-speed memory (multi-ported, multi-partitioned configuration), and flexible offload capabilities to accelerate statistics, metering, search, etc. A 15-Gb/s “GigaChip Interface” (GCI) links the devices and processors. By using 16 SerDes lanes, the solution offers an additional 200-Gb/s of full-duplex bandwidth. The companies, working on the integration/verification of the technology, plan to sample the solution in 2015.




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