Crosspoint Switch Targets I/O-Intensive Applications

By means of a non-blocking switch matrix, the MSX340 crosspoint switch can provide up to 340 individually configurable I/O ports and double-buffered configuration SRAM cells for simultaneous global updates. The foundation of the device is its silicon-efficient non-blocking crossbar architecture that uses the switch matrix to connect I/O buffers in one-to-one or one-to-many connections. Designers can configure the device's switch matrix, I/O buffers and control registers by using either the JTAG serial interface or the RapidCongfigure interface. The dedicated RapidConfigure interface has 28 pins, reportedly allowing connections to be made in less than 12 ns.
In addition, a clear-all-connections function within the interface can clear all connections from a single port. And the JTAG interface is compliant with IEEE-1149 and has five pins—TDO, TMS, TDI, TRST and TCK—that allow boundary-scan testing, as well as device configuration and verification.
Other features of the 0.35-µm crosspoint switch include an aggregate bandwidth of 25 GB/s, next-neighbor clocking of pins, tight skew, and identical pin-to-pin delays. Furthermore, the individually-configured I/O buffers can be programmed as inputs or outputs to provide bi-directional operation or to operate in bus-repeater mode. The device also allows users to select signal direction and data flow mode. Packaged in a 480-BGA, the IC costs $134 each/1,000.