Electronic Design

Electronic Design UPDATE: November 5, 2003


EDA Alert e-Newsletter PlanetEE - www.planetee.com Electronic Design - www.elecdesign.com *ALL NEW* November 4, 2003


************************ ADVERTISEMENT ************************** Synopsys' Compiler, an Online Monthly Magazine for Technologists Worldwide Compiler is an excellent source of interesting information and articles on electronic design automation (EDA), the semiconductor industry, and the electronics industry in general. Each issue of Compiler not only tackles general technology subjects, but also provides in-depth information on Synopsys' products and technologies including our latest "Great Chip Series" article which explores the development of a chip using Synopsys' design tools. To view the latest issue, please visit the Compiler website at: http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BDWZ0AC ***************************************************************** FOR THE LATEST, visit www.elecdesign.com, where the power of Electronic Design is a mouse click away! Read our Web exclusives, discover Featured Vendors, access our archives, share viewpoints in our Forums, explore our e-newsletters, and more. Be sure to participate in our current QUICK POLL: As a follow-up to our YOUR Issue, the editors ask: When the job market improves, what will you do? To take the QUICK POLL, go to Electronic Design ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK03Hf0Ak Today's Table of Contents: 1. Viewpoint Exclusive -- Bringing Hardware Emulation Performance Into The Software Domain 2. Trio Of Companies Focus On Nanometer SoC Verification 3. Accellera Elects Officers, Sets 2004 Agenda 4. Predictive Analysis Technology Accelerates Embedded Test Adoption 5. IC Package/PCB Design Flow Runs Under Linux 6. Happenings - IEEE Conference on Computer-Aided Design (ICCAD) - IP-Based SoC Design Workshop - Ansoft Global Seminars ************ 1. Viewpoint -- Exclusive to EDA Alert ************ Bringing Hardware Emulation Performance Into The Software Domain Alain Raynaud, Technology Center Director Emulation and Verification Engineering (EVE), San Jose, Calif. Each year, the EDA industry presents a bevy of verification products and solutions to circuit and system designers. These solutions are driven by ever increasing time-to-market pressures and the escalating integration and quality imposed on electronic products. For all the advantages offered by formal or static verification methods that don't require test vectors, these tools can't thoroughly test the functionality of a design. Only dynamic testing driven by testbenches can accomplish this task and, ultimately, is the only choice left to the designer. This is especially true when embedded software such as drivers, real-time operating systems (RTOSs), and custom applications must be tested. Recent technologies, like hardware verification languages (HVLs), functional verification coverage, and hardware-assisted verification, narrow the gap between designer goals and results from traditional logic verification anchored in software simulation driven by hardware-description-language (HDL) testbenches. New HVLs like Verisity's e language, Synopsys's Vera, and C/C++ libraries of test functions dramatically increase designer productivity through the number of tests generated in any amount of time. Functional-verification coverage software increases designer confidence in testbenches produced with HVLs. However, they don't address the problem of reducing the amount of time required to apply those tests, and they can't be used when developing embedded software. Only hardware-assisted verification solutions, such as hardware emulators, can accomplish the verification task within a practical time frame. Hardware emulators provide a level of accuracy, speed, and visibility to RTL simulation, albeit at an exorbitant cost. Full visibility of internal signals and embedded logic analyzers make them the tools of choice for hardware engineers. Alas, they don't interface well with embedded software and cost restricts their usage to a few high-end chip projects. Traditionally, software developers validate their code using instruction-set simulators (ISSs), though they suffer from a few limitations: They're not cycle-accurate and don't fully support interfaces to custom RTL blocks. That's why more and more software developers turn to FPGA prototypes that use JTAG ports to connect to a software debugger. Cycle-accurate code runs faster on an FPGA prototype than on an ISS. Once manufactured in small quantities to amortize the engineering cost, FPGA prototypes are fairly inexpensive to build, making them ideal vehicles for large software-development teams. Debugging hardware on an FPGA prototype can be difficult, particularly for complex SoCs that are larger than a million ASIC gates, leading to late availability of the FPGA prototype for software developers. By merging the advantages of a hardware emulator (accuracy and internal visibility) with those of the FPGA prototype (speed and low cost), a verification vehicle could be offered for both hardware design and software development. The time has come for one platform that solves the hardware/software co-verification gap. This platform would retain the hardware debugging environment of the high-end hardware emulator, but sidesteps its excessive cost. It performs at the speed of the software development board and can be controlled in software via the transaction-based technology. This "transactional emulation prototype" contains an actual implementation of the hardware design that connects to live interfaces. It's also a software-development environment that maximizes flexibility, analysis, and reuse, and sells at a cost of a perpetual software simulation license. Such a platform will offer a common ground for intellectual-property (IP) vendors and users with the potential to dramatically reduce the cost of developing SoCs. It'll also get hardware and software engineers to work together and that, in itself, is a step in the right direction. Contact Alain Raynaud at: mailto:[email protected] To comment on this article, go to Reader Comments at the foot of the Web page: Electronic Design ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BDWa0AJ ************************ ADVERTISEMENT ************************** Sponsored By: True Circuits, Inc. True Circuits, Inc. now offers a low-jitter DDR DLL that is flexible and has excellent linearity and resolution. It uses an analog delay line that is phase-locked to be insensitive to temperature or supply voltage. This silicon-proven hard macro is available for immediate delivery in TSMC, UMC and Chartered processes from 0.25 to 0.09 micron. Call (650) 691-2500 or visit: http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BDWb0AK ***************************************************************** ******* 2. News ******* Trio Of Companies Focus On Nanometer SoC Verification Verisity Ltd., 0-In Design Automation, and Novas Software will collaborate to tackle verification challenges at nanometer geometries with Verification Process Automation (VPA) tools and methodologies. The three companies will initially focus on 90-nm, 50-plus million gate, multi-CPU and embedded-software designs with well-defined processes that span the entire system-on-a-chip (SoC) verification flow, from the module to the unit, chip, system, and project-level. The group plans to define nanometer VPA flows and interfaces within their specialized areas of expertise. It also will define common data models to enable the sharing of critical process information among multiple tools. Specifically, Verisity will define the top-down, spec-driven verification management process. 0-In will define the implementation-centric "design-for-verification" flows, incorporating assertion-based and formal verification. Novas will define the debug and failure analysis flows spanning the entire top-down, spec-driven, and implementation-up range of activities, from signal to transaction level. A VPA flow based on common data models will make it easier to quickly adopt best-in-class tools. In particular, internal or third-party tools will also be able to read and use the same data to further enhance the verification process. By combining VPA approaches, new levels of automation will be possible (e.g, static with dynamic engines, random with directed or real-world testing and monitoring), yielding more optimal, scalable results. 0-In ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BDWc0AL Novas ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK071i0AU Verisity ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0paJ0Ai ******* 3. News ******* Accellera Elects Officers, Sets 2004 Agenda Accellera, the electronics industry organization focused on language-based design standards, recently announced election of officers. In addition, the organization divulged plans for the next year, which include sending the Accellera SystemVerilog design language standard to the IEEE for standardization. Dennis Brophy, director of strategic business development at Model Technology, a Mentor Graphics company, was elected Accellera's chair for a fourth term. Shrenik Mehta, director, Frontend Technologies - ASICs & Processors, Sun Microsystems, was re-elected vice chair. Dave Kelf, vice president of marketing, Novas Software, was elected treasurer. Karen Bartleson, director of interoperability, Synopsys, was re-elected secretary for a fourth term. In the coming year, Accellera plans to enhance the process it uses to build and maintain electronic design standards with the IEEE. It will also assign the copyright of SystemVerilog 3.1a to the IEEE for standardization consideration by the IEEE 1364 Working Group before the 41st Design Automation Conference in June. Accellera's technical committees have plans in place to complete the unification of Accellera's Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1, and synchronize the Accellera Verilog Analog/Mixed-Signal (Verilog-AMS) design language standard with its SystemVerilog syntax. In addition, Accellera looks forward to another successful Design Verification Conference in March 2004. Accellera ===> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK071h0AT ******* 4. News ******* Predictive Analysis Technology Accelerates Embedded Test Adoption LogicVision Inc. has debuted a tool to guide designers through the embedded test integration process. ET Planner, developed with Atrenta Inc., is used at the RTL design stage. It provides upfront guidance and compatibility verification between the design architecture and LogicVision's embedded test technologies. LogicVision believes this expert guidance will help ensure a successful integration process. ET Planner, coupled with existing RT-level LogicVision DFT rule checking, is included in LogicVision's latest LV2004 product. Designers can now make architectural decisions early in the design flow to enable the design to be optimized for embedded test. Use of ET Planner will also help to ensure that the RTL code is kept synchronized to lower-level netlist representations. The LV2004-ET Planner tool will be available early in 2004 for the Linux, Solaris, and HP-UX operating systems. ET Planner will be bundled with all Memory BIST and Logic BIST packages. For more product details and pricing, please e-mail to: mailto:[email protected] LogicVision ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0o8Y0AH ******* 5. News ******* Sequence Garners Key Post-Route Optimization Patent Sequence Design received a patent for interconnect-driven design optimization, a key technology for fast design closure below 90 nm. The technology has been deployed in the company's latest version of PhysicalStudio. U.S. Patent No. 6,591,407, "Method And Apparatus For Interconnect-Driven Optimization Of Integrated Circuit Design," describes a phased optimization methodology to speed design closure. The design is first "pre-conditioned" to ensure that no part of the circuit is operating outside of its specified range. This targets specific problem areas, or "hot spots," within the design that can be ranked using a unique algorithm to identify locations where performance improvements will have the greatest potential impact. Following this step, optimization of hold and setup time violations is performed automatically. Fixes are performed with surgical precision to minimize their impact on the layout to avoid additional iterations. The new design methodologies described in the patent include the work of co-authors, Douglas Kaufman, Dr. Vinay Srinivas, and Dr. Robert Mathews. Sequence Design ==> http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BDWd0AM ************* 6. Happenings ************* IEEE Conference on Computer-Aided Design (ICCAD) Doubletree Hotel, San Jose, Calif. November 9-13, 2003 http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK05As0As IP-Based SoC Design Workshop Espace Congres du World Trade Center, Grenoble, France November 13-14, 2003 http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BALZ0Aw Ansoft Global Seminars Cities around the world November, 2003 http://lists.planetee.com/cgi-bin3/DM/y/edSN0DJhTw0BSK0BDDh0A6 ***************************************************************** EDA ALERT e-NEWSLETTER CONTACTS


EDA Technology Editor, Electronic Design: David Maliniak mailto:[email protected] Advertising/Sponsorship Opportunities: Bill Baumann mailto:[email protected]


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