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IC Performs Complete Packet Inspection At 20+ Gb/s

Relying on a breakthrough processing architecture, the company's latest chip can perform complete packet inspection, a combination of deep-packet inspection plus header classification, at 20 Gb/s while consuming 6W. The patent pending architecture is such that processing throughput is completely deterministic, making exact throughput guarantees possible. In addition, a unique algorithm allows throughput to scale linearly with the chip area to 40 and 100 Gb/s. The chip enables intelligent network switches, routers, and network devices that are able to actively analyze and respond to network traffic based on 100% analysis of packet payloads and headers. Reportedly, it offers as much as 10 times the processing performance at one-tenth the cost of existing solutions. Employing the chip in existing and emerging designs is said to be fairly simple via its bump-in-the-wire integration model. Additionally, support is via a simple, template-based API. CPACKET NETWORKS, Mountain View, CA. (650) 969-9500.


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