Eliminating software adjustments in circuits based on digital logic improves robustness and reduces cost for small-production-run series. This circuit is a cost-improved version of classical QPSK modulator designs. Based on common CMOS logic, it needs no frequency or phase adjustments. These characteristics make the circuit suitable for such applications as factory communications.

In QPSK modulation, the bit stream of the signal to be transmitted (PCM signal) is previously sampled and decomposed into two binary waves (dibits). Each pair of dibits is associated with one of four possible phases of the QPSK modulation. The modulated signal is:

s(t) = I_{k}cos(2πf_{c}t) + Q_{k}sin(2πf_{c}t)

where I and Q are the in-phase and in-quadrature components of the modulated signal. The signal's values (1 or −1) determine four points (or symbols) in the QPSK signal space (or constellation). I and Q values are assigned according to associated dibits combinations. The classical circuitry to implement s(t) is based on the block diagram shown in Figure 1. If I and Q take their values from the set \[1,−1\], the constellation shows four points at phases 45º, 135º, 225º, and 315º. In this case, the QPSK also is called 4-QAM.

The low-cost realization of this circuit consists of rotating the angles of the QPSK constellation 135º, by increasing the set of possible values of I and Q components to \[−1,0,1\]. In this case, the table shows the modified phase distribution. These phases are easily realizable with conventional logic circuitry because the initial phase of 0º is the same as the carrier wave. The remaining phases may be obtained from simple 90º consecutive phase shifts, avoiding the mixers of Figure 1. But that comes only with a slight reduction of the signal-to-noise ratio *(Fig. 2)*.

Figure 3 is the actual circuit realization of the block diagram in Figure 2. From a main oscillator of frequency (f_{m}), a frequency divider (IC1A) supplies values of f_{m}/2, f_{m}/8, and f_{m}/16. Acceptable values of f_{m} depend on the selected CMOS technology. The circuit has been tested at f_{m} = 2 MHz with basic CMOS logic, and at 20 MHz with HCMOS.

Dibits are formed from a digital input (PCM signal) in shift register IC2B, and in the dual flip-flop IC3. The different phases of 0º, 90º, 180º, and 270º are produced at outputs QA, QB, QC, and QD of the four-bit shift register, IC2A.

Finally, the dibits (on pins A and B of IC4) control the multiplexer (data selector) output. This is a selected phase from D0, D1, D2, or D3, according to the dibit combinations. The rest of the circuit is a simple band-pass filter that eliminates dc levels and shapes the pulse, plus an amplifier to set the desired output level. The QPSK output frequency is f_{m}/8.