Over 40% of the papers presented at this year's ISSCC were communications- or networking-oriented. That was to be expected given this year's theme, "The Internet Age: Technologies Driving Digital Convergence." Memory, microprocessor, and other digital themes dominated in the past. But today, RF and wireless are the hot topics along with optical communications. This year, the focus was on the fastest growing wireless areas such as cell phones, wireless LANs, and Bluetooth.
Even as RF operating frequencies get higher and data rates for optical and other serial data continue to rise, there's a tendency to use CMOS exclusively where possible. While some biCMOS and SiGe bipolar devices are still used, it's amazing what you can do with 0.18- and 0.25-µm CMOS. You can put more on a chip and have it operate at frequencies over 40 GHz. Consequently, single-chip designs at microwave frequencies will promise lower chip cost and lower power consumption in future designs.
Perhaps the greatest challenge facing radio designers is the receiver. After looking through almost two dozen papers on single-chip UHF (800-900 MHz) and microwave (1.2, 1.8/1.9, and 2.4 GHz) receivers, some common trends and design solutions are noticeable.
Receiver architectures are a mix of conventional superheterodyne designs such as direct-conversion (zero-IF) and low-IF designs. Direct conversion is highly desirable, as it removes the need for expensive off-chip SAW filters. This design is difficult to achieve, however, since it results in dc offsets, increased flicker noise, local-oscillator (LO) feedthrough to the antenna, and LO pulling by the power amplifier (PA).
Yet some designers have conquered these problems with innovative techniques. Some direct-conversion designs presented include a single-chip 802.11b transceiver wireless LAN chip from Philips Semiconductor, Sunnyvale, Calif. (paper 13.5), a 3G WCDMA receiver from Finland's Helsinki University of Technology (paper 18.1), and a 930-MHz 4FSK receiver from the Hong Kong University of Science and Technology (paper 18.4).
Most designs use the traditional single-conversion superheterodyne approach. Popular single-IF frequencies are 190 and 200 MHz, or 120 kHz for low-IF designs. Low-IF designs avoid direct-conversion problems and eliminate the external SAW filter since on-chip filters can be implemented.
Starting with the input, most designers have settled on the cascode configuration for their low-noise amplifiers (LNA). This architecture uses two transistors in series to avoid the effects of positive feedback from output to input (Miller capacitance), which produce instability. No additional components are needed for neutralization. Inductors are used in the source (or emitter) for decoupling.
Paper 26.2, which comes from the Catholic University, Leuven, Belgium, shows a CMOS LNA using a cascode configuration for a super-low-noise GPS front-end at 1.2276 GHz. A noise figure of 0.79 dB was achieved.
Developed by the University of Minnesota, Minneapolis, paper 10.5 discusses an LNA for CDMA that offers a distinctive way to improve linearity. CDMA amplifiers must be unusually linear to minimize harmonics and intermodulation distortion. The procedure used significantly reduces harmonics (usually the third) with a cancellation process that increases linearity by 40 dB.
As for mixers, the Gilbert-cell design predominates in both bipolar and MOSFET form. A good number of the papers focus on image-reject mixer circuits. Originally developed to achieve single-sideband modulation without filters, this technique uses two sets of mixers. One receives the input signal and LO directly, while the other receives these signals shifted by 90°. By adding the mixer outputs, one sideband is cancelled. In a mixer, this means any image is rejected. This method allows a wider range of IF choices and simplifies frequency-synthesizer design. To be effective, however, the mixer circuits require precise phase and gain matching for the desired level of image rejection.
A unique clock and synthesizer for 2.4-GHz radios was used in two designs (Fig. 1). The synthesizer voltage-controlled oscillator (VCO) runs at 1.6 GHz. Its output is divided by two and the resulting 800-MHz signals are fed to I and Q mixers. At this stage, they're mixed with the 1.6-GHz signals and upconverted to 2.4 GHz for the transmitter. The 2.4-GHz receiver input is first mixed with the 1.6-GHz signal to get 800 MHz. Afterward, it's mixed with 800 MHz down to a zero IF.
Oscillator Radiation Cut
Operating the VCO far from the transmitter output prevents the direct or harmonic pulling that can occur when the VCO and PA run at the same frequency. Plus, it reduces LO radiation since the VCO output is well out of the band of operations. This design is used in the 2.4-GHz transceivers described in paper 26.6 by the EE department of the University of California, Los Angeles, as well as in the Bluetooth transceiver introduced in paper 13.3 by Broadcom, El Segundo, Calif.
IF filters are still predominantly SAW at higher frequencies because of their excellent selectivity. Yet designers seek every opportunity to exclude them because of their cost and the pc-board space they eat up. In direct-conversion and low-IF designs, on-chip filters can be used. These typically polyphase active filters use op amps and RC networks made with polysilicon resistors and metal-insulator-metal (MIM) capacitors.
Most receiver circuits use LC filters for some selectivity. On-chip spiral inductors can achieve Qs up to about 12. Some designs actually use bonding wires for inductors.
In transmitters, most designs use direct conversion, translating the baseband directly to RF with quadrature upconverters. The most critical part of the transmitter, especially for CDMA, is the power amplifier (PA). It must be very wideband and extremely linear to prevent intermodulation distortion. Common designs include Class A and AB, with some kind of feedback to enhance linearity.
For designs using frequency modulation, however (i.e., GSM and Bluetooth), nonlinear Class C, D, E, or F amplifiers are used for greater efficiency. In cell-phone applications, a way to vary the output power is required as well.
Two papers on PA design use the Class F amplifier, a switching type that yields good efficiency. Normally, a single-stage and a tuned circuit or quarter-wave transmission line in the output are used to enhance the odd harmonics for faster switching.
A design (paper 10.1) from Philips Semiconductor, Milpitas, Calif., uses a cascode circuit in which the transistor between the amplifier and the supply voltage has a thicker oxide. This allows for a higher breakdown voltage with small-geometry CMOS. With a higher supply voltage, higher output power is achieved. In addition, the cascode design furnishes a convenient way to control output power by adjusting the bias on the cascode transistor.
Paper 10.2, submitted by the Center for Integrated Systems, Stanford University, Calif., discusses a PA that uses three parallel Class F power amplifiers and quarter-wave transmission lines to combine the outputs. In this design, the transmission lines don't just supply harmonic waveshaping in the Class F circuit, they also provide the isolation between amplifiers. The impedances of the transmission lines are binary weighted (1-2-4) and give the effect of a digital-to-analog converter (DAC). Individual power amplifiers may be turned off or on to adjust the power in eight steps without disturbing the circuit impedances.
Many companies have been working on Bluetooth designs during the past year. Putting a Bluetooth radio in silicon leads to some interesting options and designs. The ideal implementation is a complete single-chip solution that incorporates the analog RF transceiver as well as the digital baseband section, leading to the lowest-cost solution. But combining both the analog RF and digital circuits on one chip is tough.
Paper 13.1 describes a complete one-chip Bluetooth transceiver designed by Alcatel Microelectronics, Zaventem, Belgium. The device offers a transmitter and receiver, baseband processor, embedded controller with RAM, and flash memory. The only external components are the crystals for the frequency synthesizer and the antenna.
To allow on-chip polyphase RC active bandpass filters to be used for selectivity, the receiver employs image-reject mixers and an IF of 1 MHz. Using the on-chip analog-to-digital converters (ADCs), the quadrature outputs are demodulated and converted to digital.
The transmitter section is a direct-conversion type. Via the on-chip PA, up to 2 dBm of power is generated into a 75-W symmetrical-load antenna.
Contained in the integrated frequency synthesizer is a VCO operating over the 4.8- to 5-GHz range, which is twice the operating frequency. This minimizes parasitic coupling between the PA and VCO. The phase-locked loop (PLL) is locked to an external 13-MHz crystal.
Making up the rest of the chip's circuitry are the embedded controller, the digital baseband processor, and data interfaces. The embedded controller is an ARM7 with 48 kbytes of RAM, 256 kbytes of flash, and a small boot ROM.
For the remaining Bluetooth chips covered, only the radio part of Bluetooth is discussed. All of these chips strive to minimize power dissipation and the number of external components required. Authors from the Institute of Microelectronics in Singapore contributed paper 13.2. They presented a device that integrates the entire transceiver (except a bandpass filter at the antenna), a crystal to set the synthesizer frequency, and an off-chip loop filter for the PLL.
In paper 13.3, Broadcom describes a Bluetooth transceiver as well. The only external components are a matching capacitor for the LNA, a 12-MHz crystal for the synthesizer, and several bias resistors.
Paper 13.4 features a Bluetooth transceiver developed by Conexant of Nepean, Ontario, Canada. Its primary claim to fame is its exceptionally low-power consumption. This attribute is key to most Bluetooth applications, the majority of which are battery powered. With a 2-V supply, power consumption averages 22 mW with a current drain of only 16.4 mA while receiving.
Three papers on orthogonal frequency-division multiplexing (OFDM) show the growing acceptance and applications of this esoteric and complex modulation/multiplexing approach. OFDM is used in DSL, but it's called dual multitone (DMT). It has been proposed as an alternative to the 8VSB modulation used for HDTV in the U.S. This is because it appears to be more robust and forgiving in serious multipath applications, such as those involving indoor antennas. Its biggest use may be in wireless LANs, though, where it is the modulation of choice for the IEEE-802.11a standard. OFDM designs also are superior in applications where considerable multipath problems are encountered inside buildings.
Paper 21.4, composed by Fujitsu Laboratories Ltd. of Kawasaki and Kanagawa, Japan, details an OFDM demodulator for Japanese digital terrestrial television broadcasting (DTTB). This service is expected to be launched in 2003.
Two papers discuss OFDM modems for the 802.11a standard, a wireless LAN for the 5-GHz ISM band. Currently, 802.11b (2.4-GHz) wireless LANs are very popular. As the 2.4-GHz band gets more crowded, however, wireless LANs are expected to eventually migrate to 5 GHz.
Paper 21.5, by researchers at IMEC, Leuven, Belgium, describes a complete transceiver IC. It performs all of the DSP needed for OFDM coding and decoding as defined by 802.11a or for the European equivalent Hyperlan/2 standard established by ESTI. The chip works with an external DAC (transmit) and ADC (quadrature receive). In the transmit mode, the serial data is mapped into multiple streams of up to six bits per carrier. BPSK, QPSK, 1-QAM, or 6-QAM is used, depending on the desired transmission speed. A 64-subcarrier inverse-FFT section produces the desired signals.
Next, the receiver takes the IF signal, digitizes it using the external ADCs, and sends the signals to the chip for decoding and recovery in the FFT section. The chip achieves the 802.11a speed of 54 Mbits/s and up to 72 Mbits/s after coding within a 20-MHz bandwidth.
Paper 21.6 by Radiata, North Ryde, Australia, defines an 802.11a PHY modem that's similar, except it offers an on-chip ADC and DAC. The chip is part of the chip set used in the Radiata Communications 802.11a wireless LAN interface.
Transmission of digital data by fiber-optic links continues to grow with the demand for more bandwidth. SONET fiber-optical systems, which carry the bulk of Internet backbone traffic, are being more widely adopted for new WAN and MAN expansions. Most SONET systems today run at OC-3 (155-Mbit/s) or OC-12 (622-Mbit/s) speeds. But OC-48 (2.5-Gbit/s), OC-192 (10-Gbit/s) and OC-768 (40-Gbit/s) systems are increasingly being developed. The primary holdup has been ICs that perform all of the various serial/parallel conversions (SERDES) and other processes at line speeds. Many papers this year introduced chips that meet this need.
First, a half dozen papers feature various clock-and-data-recovery (CDR) chips for optical applications. SONET's synchronous nature makes reliable and accurate clock and data recovery very important. The CDR process is tough even at the lower speeds. But it becomes a major task in OC-48, OC-192, and OC-768 systems.
Most CDR chips use a PLL along with a half-rate phase-detector circuit to do this. A half-rate phase detector uses parallel circuits clocked by multiple phases from a clock running at half the bit rate. This alleviates the need for a bit-rate clock on-chip.
Paper 5.1, by Bell Labs/Lucent Technologies of Holmdel, N.J., describes a clock-recovery circuit and demultiplexer that uses a half-rate phase detector to recover the 2.5-Gbit/s clock in an OC-48 system. Working with a 1.215-GHz reference clock, the phase detector feeds an on-chip loop filter. The filter capacitor is 1 nF but is multiplied to 40 nF by an active loop. Jitter produced by the VCO is less than 13 ps rms.
Paper 5.3 tells of a 10-Gbit/s CDR circuit developed by the EE department at UCLA. This circuit regenerates the 10-Gbit/s (9.95328 Gbits/s actual) clock. With a pseudorandom data sequence, the jitter is 9.9 ps p-p and 0.8 ps rms.
In paper 5.6, Lucent Technologies' Optical Networking Group in Nuremberg, Germany, introduces a fully integrated 40-Gbit/s CDR and demultiplexer circuit. This IC is made with SiGe heterojunction bipolar transistors (HBTs) with an fT of 72 GHz.
Optical-processing chips covered at the conference ran the gamut from optical input amplifiers to fast serial processing circuits and laser-diode driver circuits. Paper 14.4, from the Department of Electrical and Computer Engineering at the University of Toronto, focuses on a 75-Mbit/s optical receiver that uses a common-gate transimpedance amplifier and operates from a 1-V supply.
Three papers concentrate on Sonet transceiver chips. Broadcom's paper (5.2) presents a fully integrated CMOS OC-48 transceiver. The others, 5.5 from Hitachi, Tokyo, Japan, and 5.4 from Lucent Technologies, illustrate a SiGe biCMOS OC-192 transceiver. A CDR circuit along with a 1:4 demultiplexer and a 4:1 multiplexer are included in the first circuit. The transmitter takes four serial inputs at 622 Mbits/s in 4-bit chunks and sends them to the FIFO. This compensates for any phase variations between the on-chip clock and the input clock derived from the LVDS input data.
A clock multiplier unit (CMU) obtains the external reference clock and multiplies it by 16 or 23 to get the 2.5-GHz (2.488 GHz actual) transmit clock. If forward error correction (FEC) is used, the clock frequency also can be set to 2.666 GHz. The multiplexer generates the single 2.488- or 2.666-GHz output data stream.
In the receiver, a CDR regenerates the clock from the input data stream. A demultiplexer takes the single input bit stream and regenerates the four 622-Mbit/s signals at the outputs.
Hitachi's 10-Gbit/s transceiver suits OC-192 Sonet applications, or possibly 10-Gbit Ethernet products. This transceiver multiplexes 16 622-Mbit/s data paths into a single 10-Gbit/s (9.968 Gbits/s actual) OC-192 signal. As in the previous design, a FIFO compensates for phase differences.
In the receiver, the 10-Gbit/s serial input is passed through the CDR and then to a 1:16 demultiplexer to recover the 16 622-Mbit/s signals (Fig. 2). The receiver also has an error detector and a pseudorandom bit stream (PRBS) generator for test purposes. The high speed is obtained by using HBTs made with SiGe on the inputs and outputs and MOSFETs on the internal circuitry.
Some other papers include two on Gigabit Ethernet transceivers by Marvel Semiconductor, Sunnyvale, Calif.; two on DSL analog front ends by Texas Instruments, Dallas, Texas, and Infineon Technologies, Munich, Germany; a universal set-top box on a chip by Broadcom; and a direct-access-arrangement (DAA) chip for use in the PSTN by Silicon Labs, Austin, Texas.