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Electronic Design

Transceiver Chip Replaces Parallel Backplanes With High-Speed Serial Links

Device hands designers a way to reduce bottlenecks in network and computer systems.

With parallel backplanes plagued by a variety of problems, new serial architectures are poised to take over in high-end network and computer systems. Fortunately, along comes the 21Z01 OctalPHY transceiver, which facilitates the design of high-speed serial backplanes. It can reduce hundreds of parallel backplane pins to a few serial connections. Engineers can use the chip to scale their designs and, according to the company, achieve any level of bus performance by adding as many serial links as needed.

Essentially, the 21Z01 is an eight-channel transceiver chip that takes a parallel bus (input and output buses) and converts it to a very-high-speed serial bit stream. This device from AANetcom Inc. can convert a 160-bit-wide parallel backplane operating at 125 MHz into 16 differential-pair serial connections, each operating at up to 1.56 Gbits/s. Its key functional blocks include a clock synthesizer, 8B/10B (8-bit/10-bit) encoder, serializer/deserializer, clock recovery, byte aligner, 10B/8B decoder, and two FIFO memories.

Figure 1 shows one of the eight channels of AANetcom's 21Z01 broken out into some detail. Ten bits of information come into the device. Actually, 5 or 10 is shown because a user can communicate 10 bits over just 5 pins using a dual data-rate technique. The data goes into a short FIFO and and then moves onto an 8B/10B encoder.

That encoding technique maps the 8 bits of user data into 10 bits that will actually be transmitted. The goal is to eventually recover a clock from the serial data stream by noticing the locations of its transitions. Doing so requires a minimum density of transitions in the data. In other words, the data cannot stay at 0 or 1 forever. The 8B/10B encoding provides that assurance. For every 8 bits of user data, 10 bits of information are created and transmitted. This is serialized and converted from its parallel form to the high-speed serial stream. At its input, the serializer requires a 1.25- to 1.6-GHz clock (not shown).

"It is not a trivial undertaking, of course, to create a clock that fast," says Joel Dedrick, vice president of business development at AANetcom."And we don't ask the user to do that for us. Internally, we have a phase-locked loop that takes the low-speed clock provided by the user and creates the needed high-speed clock that we use to transmit this data."

The differential output is the resulting serial data stream. This can drive either the backplane directly or a fiber- optic transceiver. In the reverse process, the high-speed serial input from another 21Z01 enters the chip through the differential input. The first step is to recover the clock, which means observing the data stream and extracting a clock from it that's suitable for capturing every one of the incoming bits. "The incoming bits at these data rates only last 700 or 800 picoseconds," states Dedrick, "so capturing them into a register is no small feat."

After the capture, deserializing occurs. The serial data converts back to 10-bit parallel data words. Then, the reverse of the encoding process returns to the originally transmitted 8-bit byte of user information. This goes into a FIFO.

The purpose of the FIFO is twofold. The eight channels shown could all potentially be arriving from different sources, thereby coming in at slightly different rates. According to Dedrick, "It's a little bit of a mess for the user to be handling eight streams of data coming in at slightly different clock rates. So we provide, as a convenience, a FIFO that can line all of those data up on the user's local clock and hand them off as one single, 80-bit entity transferred over to the user's local clock domain. That makes the design job on the other side—the chip that sits just to the left of this one—much easier."

Secondly, the FIFOs are needed in trunking applications, such as inter-campus networks. In this type of application, the 21Z01 provides the high-bandwidth trunk between two buildings. All eight channels need to be synchronized so that the data going in one side comes out aligned on the other side.

Even if the propagation delays of the serial media between buildings aren't exactly matched, Dedrick points out that the user still expects the data that went in together to come out together. The FIFOs actually have a trunking mode that allows them to cooperate with each other and make sure that the data comes out lined up correctly.

The 21Z01 OctalPHY fits into a package that's only 1.5 cm on a side. It's manufactured using a standard CMOS process, and consumes just 1.25 W with a 2.5-V supply.

Though that low power dissipation is important now, it becomes even more so in the future. The company is using a macrocell version of its serial technology to design custom chips, such as systems-on-a-chip. "We are currently engaged with customers on projects that will put large numbers of these channels on a single chip. If each one of them consumes a watt, you don't get very many before that chip melts," states Dedrick. "It's terribly important for us to drive the power per channel down to the lowest possible value, so that when we get to the system-on-a-chip integrations we can have a manageable thermal dissipation in the chip. And we've achieved that. We've hit a level of about 100 mW for each gigabit channel."

The company sees applications for the chip in a few main categories. It can target Internet routers and network switches, servers and workstations, and inter-campus networks.

A 32-Gbit/s switch is a typical example of how the 21Z01 can be used (Fig. 2). In this example, every piece of data that enters the switch eventually goes through the switch card and is then directed to its final destination. A number of line cards (four are shown here) are the interfaces to the outside world. The application is simply to move data over the backplane (shown on the left hand side of the diagram) between the line cards and the switch card. The serial backplane not only reduces pin count, but power consumption, too. A parallel backplane might contain 640 pins and use 12 W of driver power, while the serial backplane—consisting of four 21Z01s—would contain 128 pins and consume only 2 W of power.

If you take a look at the line cards themselves, you'll see that these also represent an application for the 21Z01. Suppose you wanted to build a line card that produced eight gigabit Ethernet channels. The conventional way to do this is to use a MAC (media access controller) and some number of discretely implemented functions, which result in the external interfaces. AANetcom can replace all that logic with a single 21Z01. AANetcom says the device provides a uniquely dense and low-power solution on the front side—on the customer-visible side of the box—where he sees these gigabit Ethernet ports and he hooks them up to his network.

Overall, the concept of the OctalPHy device is to put more bandwidth through fewer pins, which AANetcom regards as a huge benefit to customers. One 21Z01 replaces up to 80 bits of a bus. Each one of the device's channels takes 10 bits in and produces a single bit stream out. The net result is that 80 parallel bits are reduced to eight serial outputs.

This is a scalable technique. The company asserts that there's no inherent limit to how many lines can be used in one serial link and how fast that serial link can go. It plans a rapid advance of the bit rate. Subsequent products are going to start at 2.5 Gbits/s and go up from there. Says Dedrick, "That indicates to our customers that we are going to stay with their needs for a few generations, rather than run into a wall."

Price & Availability
The 21Z01 is sampling now with full production scheduled for March. In quantities of 1000, the device is priced at $48 in a 208-pin, 15- by 15-mm BGA package.

AANetcom Inc., 6868 Santa Teresa Blvd., San Jose, CA 95119; (408) 360-8800; fax (408) 360-8801; e-mail: [email protected] com;

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