Electronic Design

Build A "Cycle-Stealing" Ratio Divider

In many applications, requirements to produce multiple individual frequencies would indicate the usage of a phase-locked-loop (PLL) circuit approach. However, PLLs contain analog circuitry that in some cases may be undesirable.

This idea presents a novel yet simple technique, using standard digital counters that will produce discrete frequencies with jitter and inaccuracies comparable to those of a typical PLL implementation. Of course, not all designs require a 100% rock-steady frequency.

When considering alternative approaches to PLLs, a purely digital approach also is possible. A direct-digitalsynthesis (DDS) IC will, in many cases, solve the problem very nicely and accurately. But, these ICs often require a relatively high reference frequency.

Typical PLL solutions, on the other hand, inherently create a jitter component. Another possibility—fixed-frequency dividers—can only generate a fixed number of possible output frequencies.

If slight accuracy errors and jitter errors are tolerable in the target application, then a modified fixed-divider approach can be used. The “cyclestealing” ratio divider will modify the reference frequency by cycle stealing (i.e., once in a while it steals one of the clock cycles) (Fig. 1).

This method will allow a very high degree of freedom in selecting the frequency division factors. If our divisor is 10 and we “eat” one clock of each 20, then we will actually divide by 10.5. Eating one clock of each 30 will produce a division by 10.333.

Even better still, the hardware requirements are simple (Fig. 2). Using two timer-counter channels of an Intel 8254 (a three-channel programmable interval timer), the first counter (:M) is set up in the “rate generator” mode (mode 2). The second counter (:N) is set up in the “square-wave” mode (mode 3).

The drawback to this method is, of course, that the resolution drops as the divisor factors get smaller. Therefore we must keep the divisors to 16 bits. This is okay for the N divisor, but the M divisor will have to be limited, which adds to the general error in the output frequency.

The basic formula for output frequency:

now becomes:

Or we can eat some fraction of the basic clock pulses to get:

Reduce this to get:

and finally:

So now we may divide by fractions.

To determine the divider values:

NN = f / fO
Frac = (NN − N) * fO

We can’t divide by 0, so this means that we should disable M or use the highest possible M value:

IF Frac = 0 THEN
M = 65535
M = INT(f/Frac)
IF M > 65535 THEN M = 65535 ;Limit to 16-bit

The resulting output frequency will now be:

FOUT = (f / N) − (f / (M * N))

Using this method, the error will increase with frequency, because the dividers get smaller. The error is approximately:

Frequency error = (fO / 40000) ^ 3 (for f = 8 MHz )

When computing the M and N values for your microprocessor, be careful NOT to overflow the 16-bit capacity of the dividers. The calculations provided (see the table) show some of the frequencies and their associated errors for f = 8 MHz.

If your frequency requirement lies in the audio band from 50 to 20,000 Hz, then the maximum fO deviation will be 0.3 Hz. The small BASIC program (see the listing) is helpful when computing the dividers.

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