In the S3050 clock and data-recovery IC, designers will find a device capable of supporting OC-3, OC-12, Gigabit Ethernet and OC-48 frequencies. The device is said to achieve the high speeds and meet the performance requirements for the industry's converging data communication and telecommunication markets while complying with ANSI, Bellcore and ITU-T specs for jitter tolerance, jitter transfer and jitter generation. The chip supports clock recovery for OC-3, OC-12, Gigabit Ethernet and OC-48 NRZ data and uses an on-chip PLL consisting of a phase detector, loop filter, and VCO. The phase detector compares the phase relationship between the VCO output and serial data input and the loop filter converts the phase detector output into a smooth dc voltage. The VCO frequency is then varied by this dc voltage input. A lock-detect function monitors the integrity of the serial data inputs from the chip.