EE Product News

Clock Drivers Work At 3.3V

Targeted for use with SDRAM registered DIMMs, two new PC-100 3.3V SDRAM PLL clock drivers have been developed to provide precise phase and frequency alignment of their clock outputs to an externally applied clock input. QS52509A and QS52510A devices are designed to interface with high-speed SDRAMs rated up to 160 MHz. An on-chip 25 ohm resistor reduces ground bounce noise. The internal loop filter guarantees excellent jitter characteristics of ±100 ps maximum and eliminates the need for external components. The devices are said to offer guaranteed low skew and low jitter between all 10 and 11 outputs, respectively, and to also feature balanced drive outputs of ±12 mA, 5V tolerant inputs and operation from 3V to 3.6V over a temperature range of -40°C to 85°C.


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