Electronic Design

Dual-Regulated Voltages Control STN-LCD Contrast

Generating a stable, dual-voltage, LCD-contrast supply can be difficult, particularly if the two voltage amplitudes must track each other with respect to a given reference level. In Figure 1, the ±20 V outputs are centered on a 3-V reference level (VM). The contrast voltages must be symmetric about VM to avoid creating a dc component across the liquid crystal. If this were to occur, it would damage the LCD or shorten its life.

Figure 2's arrangement provides a triple-output, regulated LCD supply, which produces a main supply voltage and two LCD voltages symmetric around the LCD offset voltage (VM). To achieve this, four Schottky diodes (D1 to D4) and two flying capacitors (C2 and C3) were added to a dual-VOUT circuit. U1 normally supplies a digital VMAIN (typically 3.3 V) and an LCD supply (up to 28 V). Here, the ±LCD output equals VM ± LCDREF.

U1 is a high-efficiency, dual-output boost converter for portable devices needing two regulated outputs. Operation with inputs as low as 0.7 V allows it to accept one-, two-, or three-cell alkaline, NiCd, or NiMH batteries, as well as one-cell Li-ion batteries. It requires no external switching FETs and draws only 20 µA of supply current, making it ideal for handheld PDAs and pen-input devices.

A switching FET internal to U1 repeatedly connects LCDLX (pin 12) to ground and then releases it. As a result, the LCDLX voltage toggles between ground and LCDR plus one diode drop (LCDR is the LCDREF output). This action, similar to that which produces the VMAIN output at pin 16, generates the ±LCD voltages as follows:

In phase 1 (−LCD output), the rise of LCDLX voltage to LCDREF + VDIODE forces voltage on the other side of C3 to VM + VDIODE. Doing so creates a differential voltage of LCDREF − VM across C3. The LCDLX voltage is the reference point. During phase 2, as LCDLX goes to ground, the load side (−LCD OUT) sees a voltage equal to −LCDREF + VM. This drives current from the −LCD load through D4. When this current flow discharges C3 slightly, the cycle starts again. Note that the +LCD and −LCD outputs develop on alternate phases. The resulting −LCD voltage is:


In phase 2 (+LCD side), when LCDLX goes to ground, the load side of C2 sees a voltage equal to VM − VDIODE. Then, phase 1 takes place. The rise of LCDLX to LCDREF + VDIODE forces a voltage of LCDREF + VM on the other side of C2. The +LCD load also sees an additional diode drop across D5:


These load equations show that −LCD OUT and +LCD OUT track each other with respect to LCDREF (Fig. 3). They're offset from VM by less than one diode drop.

Schottky iodes D1 to D5 can be EP10QY03 or MBR0530 types. C2 and C3 can be 1 µF, preferably with voltage ratings of at least 2 × LCDREF. Typical L1 and L2 values are 10 µH each. The output capacitors (C4 to C6, shown as 10 µF) may be sized according to the allowable output ripple.

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