Electronic Design UPDATE: April 6, 2005

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Electronic Design UPDATE e-Newsletter
Electronic Design Magazine
PlanetEE ==> www.planetee.com
April 6, 2005
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Today's Table Of Contents:
1. Editor's View
  *Test Emerges As An EDA Battleground
2. Focus On ASICs
  *Improved Smart Power Process Shrinks Mixed-Signal Chip Size
3. News From The Editors
  *16-Bit DAQ Board Has Flexible Inputs
  *Graphics Processor Offers PCI Express Interface
  *ISA Committee Focuses On Wireless Technology
4. Magazine Highlights: March 31, 2005
  *Cover Story: Engineering Feature -- Getting To A Higher Level
  *Technology Report -- Smarter Antennas Breed Success In Wireless 
   Arena
  *Leapfrog: First Look -- Build A Board In-House Without The Mess
  *Design View/Design Solution -- Roll Your Own Custom x86-Based 
   Embedded Systems

Electronic Design UPDATE edited by Lisa Maliniak, eMedia Editor

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1. Editor's View -- Exclusive to Electronic Design UPDATE
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Test Emerges As An EDA Battleground

By David Maliniak, EDA Editor

As noted by some observers, the EDA industry's attention is shifting 
away from the center portion of the IC design cycle (RTL design), 
which has become very much commoditized, and toward the extreme 
front and back ends of the process. At last month's Design 
Automation and Test in Europe (DATE) Conference in Munich, vendors 
certainly made a great deal of effort to highlight their electronic 
system-level (ESL) methodologies 
( http://nls.planetee.com/t?ctl=6D5B:1001CD ). To be sure, 
ESL is emerging as the Great Hope for closure of the verification 
gap that only grows wider with each new downward step into the 
nanometer realm.
   Among other things, ESL methodologies target validation of system 
architectures, a growing concern in this age of platform-based 
design and heavy intellectual-property (IP) reuse. But the 
ongoing shift to nanometer process technologies brings up other 
issues that are much more related to the back end, meaning 
testability and, ultimately, yield. The battle among EDA vendors 
for the hearts and minds of designers with regard to how they 
achieve testability of their designs is just beginning. As more 
design teams find themselves compelled, for want of greater 
functional integration, to move down the nanometer scale, they'll 
quickly learn that their existing test methodologies aren't going 
to cut the mustard.
   Each new generation of process technologies has seen adoption of 
very different test strategies, each of which targeted different 
primary fault mechanisms. In the days of relatively spacious 
design rules of 0.25 microns and higher, a functional test model 
was sufficient to flag problems. For today's mainstream 180-nm 
processes, a stuck-at fault model is the primary mechanism used 
to ferret out hard, static failures that result when any given 
node in a design is "stuck at" zero or one. Automatic 
test-pattern generation (ATPG) tools are typically used to 
generate static test vectors to detect such faults.
   Move below 180 nanometers, though, and stuck-at methodologies 
become a liability, just as functional test models are at 180 nm. 
New classes of fault mechanisms appear at nanometer geometries, 
such as resistive shorts, resistive opens, and bridges, none of 
which can be detected with stuck-at testing. These are primarily 
speed-related failures, or, as they're sometimes called, at-speed 
failures. Resistive nodes or bridges can cause given nodes to be 
slow to rise or fall, but they still rise or fall, nonetheless, 
which is why such faults can cause errors in high-speed circuits 
but still pass static stuck-at tests. They won't cause the 
circuit to completely fail to change states, but rather, they 
royally screw up your timing.
   So the industry finds itself moving to a new test paradigm of 
transition fault models. Such models test whether the circuit is 
transitioning properly or not between logic states. Transition 
delay fault models determine if the delay between two logic 
values is acceptable. And, path delay fault models test for 
delays along a predetermined path caused by RC coupling with 
other paths. None of these failures, by the way, will show up 
using stuck-at testing.
   DATE saw a pair of significant announcements in the test arena, 
both of which purport to address this ongoing test-methodology 
shift. Cadence Design Systems ( http://nls.planetee.com/t?ctl=6D6B:1001CD )
rolled out another pillar of its Encounter test strategy with 
the release of Encounter Test Architect. All designers need to
insert a test infrastructure into their designs. Today, this 
requires disparate tools for creation of the various flavors of 
test, including scan chains, memory built-in self-test, IP core test,
I/O test, and others. Further, these tests typically require 
manual creation of the connectivity that ties them together.
   Encounter Test Architect is based on full-chip compilation of 
test infrastructure, which automates this entire process. It 
couples nicely with Cadence's earlier Encounter True-Time Delay 
Test, which creates tests based on actual SDF post-layout timing 
as opposed to traditional delay testing that simply tests at the 
system clock speed. Cadence's approach accounts for the fact that 
some paths are longer than others, some shorter, and some are 
multicycle paths.
   Synopsys ( http://nls.planetee.com/t?ctl=6D6A:1001CD ) 
chose DATE to debut its DFT Compiler MAX, a next-generation
design-for-test (DFT) synthesis tool that offers one-pass test
data volume compression. DFT Compiler MAX uses what Synopsys 
calls "adaptive scan" technology to generate an efficient 
scan architecture, which leads to minimum test application time.  
It enables compression of both stuck-at and at-speed tests.
   The announcements show that test is indeed on the radar screens 
of the EDA industry's biggest players and that promising 
technologies are appearing to help address the test issues that 
arise at nanometer process geometries. There's little doubt that 
more tools and technologies along these lines will surface in 
June at this year's Design Automation Conference. 

To comment on this Editor's View, go to Reader Comments at the foot 
of the Web page:

Electronic Design UPDATE ==>
http://nls.planetee.com/t?ctl=6D5A:1001CD

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2. Focus On ASICs
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***Improved Smart Power Process Shrinks Mixed-Signal Chip Size
An enhanced Smart Power mixed-signal process technology developed by 
AMI Semiconductor (AMIS) significantly reduces transistor 
on-resistance by up to 25%. The reduction in on-resistance improves 
transistor efficiency, enabling the creation of devices with higher 
power capabilities or with smaller transistor sizes for the same 
power. The process helps reduce the size of mixed-signal ASICs and 
application-specific standard products employed in a wide variety of 
automotive, industrial, and computer peripheral applications. AMIS's 
I2T100 (Intelligent Interface Technology) mixed-signal technology 
includes 40-, 60-, and 100-V high-voltage transistors based on 
0.7-micron mixed-mode CMOS. A single IC can combine low-, medium-, 
and high-voltage circuitry; high-precision analog circuitry; 
nonvolatile memory; and some medium-complexity digital logic. 
Embedded power switches, H-bridge circuitry, and other applications 
requiring higher current draw (up to 5 A) will benefit most from 
this enhanced transistor technology.
     AMI Semiconductor ==> http://nls.planetee.com/t?ctl=6D6C:1001CD

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3. News -- From The Editors
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***16-Bit DAQ Board Has Flexible Inputs
The PCI-1747U data-acquisition card features 16-bit resolution and 
can run at 250 ksamples/s even when different ranges are used on its 
64 input channels. This is possible because of an onboard scanning 
circuit that controls multiplexer switching during sampling in a way 
that is more efficient than a software implementation. The circuit's 
SRAM stores different gain, single-ended versus differential, and 
bipolar versus unipolar values for each channel. Also, a built-in 
autocalibration feature reduces calibration downtime to a matter of 
seconds. Other standard features include Advantech's BoardID switch 
and plug-and-play function for easier configuration as well as a 
universal PCI interface that supports both 3.3 and 5 V. Device 
drivers are available for Windows XP, 2000, and 98. ActiveX control 
for VB.NET and C#.NET programming tools and a LabVIEW driver are 
also available for free. The PCI-1747U costs $995 and is available 
directly from Advantech or through one of its North American 
distributors.
     Advantech ==> http://nls.planetee.com/t?ctl=6D68:1001CD

***Graphics Processor Offers PCI Express Interface
Armed with PCI Express as its host interface, the GammaChromeS18 
graphics processor plans to invade the mainstream graphics market. 
S3 Graphics' chip incorporates hardware digital video accelerators 
and supports DirectX 9.0 3D graphics along with the company's Hi-Def 
native HDTV display capability. There's also support for all of the 
latest displays, including multiple screen configurations. The PCI 
Express interface handles either eight- or 16-lane operation for a 
maximum throughput of up to 8 Gbytes/s. Capable of 500-MHz clock 
speeds, the GammaChromeS18 series includes an enhanced version of 
the company's Chromotion programmable video engine. The Chromotion 
2.0 engine performs line doubling using an adaptive de-interlacing 
scheme that does a per-pixel analysis of the video stream in real 
time. Chromotion 2.0 also includes ArtisticLicense, a real-time 
video-effects and filtering capability. Contact the company for 
volume pricing. 
     S3 Graphics Co. Ltd. ==>  http://nls.planetee.com/t?ctl=6D69:1001CD

***ISA Committee Focuses On Wireless Technology 
A new Instrumentation, Systems, and Automation Society (ISA) 
standards committee, ISA-SP100, will work to create standards, 
recommended practices, and/or technical reports to define procedures 
for implementing wireless systems in the automation and control 
environment. The committee will address various aspects of wireless 
manufacturing and control systems technology, including the 
environment in which it is deployed, the technology life cycle, and 
applications. The committee chair explains that the new standards 
will ensure successful system deployment, address any 
vulnerabilities, and improve overall system performance by 
eliminating failure modes. Committee members include representatives 
from Adaptive Instruments Corp., Honeywell, Motorola Labs, Oak Ridge 
National Laboratory, Oceana Sensor, Omnex Control Systems Inc., 
Shell, and a variety of other companies.
     ISA ==> http://nls.planetee.com/t?ctl=6D66:1001CD

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4. Magazine Highlights
**********************
In case you missed them, here are some of the high points of our 
most recent issue.

March 31, 2005:

* Cover Story: Engineering Feature -- Getting To A Higher Level
As SystemVerilog and SystemC embrace system-level verification, they 
bring broad implications for design methodologies and tool flows.
http://nls.planetee.com/t?ctl=6D59:1001CD

* Technology Report -- Smarter Antennas Breed Success In Wireless 
Arena
Spatial-diversity, MIMO, and advanced-array techniques juice up 
wireless performance.
http://nls.planetee.com/t?ctl=6D5E:1001CD

* Leapfrog: First Look -- Build A Board In-House Without The Mess
Novel technology moves pc-board prototype creation into the office.
http://nls.planetee.com/t?ctl=6D5D:1001CD

* Design View/Design Solution -- Roll Your Own Custom x86-Based 
Embedded Systems
http://nls.planetee.com/t?ctl=6D5C:1001CD

For the complete Table of Contents, go to Electronic Design ==>
http://nls.planetee.com/t?ctl=6D60:1001CD

*****

BE SURE TO VISIT Electronic Design's Web site, where the power of 
Electronic Design is a mouse click away! Read our Web exclusives, 
enjoy our Quick Poll, discover Featured Vendors, access our 
archives, share viewpoints in our forums, explore our e-newsletters, 
and more.

*****

Overcoming "The Fiefdom Syndrome": How to Conquer the Turf Battles 
that Undermine Companies

Can your organization benefit by overcoming turf battles? 

Don't miss this opportunity to hear Robert J. Herbold, former COO of 
Microsoft and author of "The Fiefdom Syndrome," and Jim Davis, 
Senior VP, SAS.

Join Business Finance in welcoming these thought leaders on Tuesday, 
April 19 at 11 a.m. EDT. Register here:
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*****

THOUGHT YOU'D MISSED THEM? DON'T WORRY, THEY'RE ARCHIVED
Electronic Design's webcasts are available online:
COM Express -- Emerging Standard: Explore the new Computer-on-Module
standard from the PICMG. http://nls.planetee.com/t?ctl=6D67:1001CD

Next-Generation In-House PCB Prototyping: Produce your own PCB 
prototypes without the use of hazardous chemicals.
http://nls.planetee.com/t?ctl=6D61:1001CD

Advances In Signal Integrity Testing: Michael Lauterbach of LeCroy 
Corp. describes advances in testing for signal integrity.
http://nls.planetee.com/t?ctl=6D67:1001CD

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CONTACTS: Electronic Design UPDATE e-NEWSLETTER
==================================

Editorial: Mark David, Editor-in-Chief
mailto:[email protected]

Advertising/Sponsorship Opportunities: Bill Baumann, Publisher:
mailto:[email protected]
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