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SCGs Replace Discrete-Designed PLLs

Designed to replace PLLs that have been designed with discrete devices, the SCG Series of synchronous clock generators (SCGs) can accept an input reference signal at one frequency and deliver a jitter-reduced, phase-coherent signal at a higher frequency. A typical representative of the SCG Series is the SCG200, a digital phase lock loop (PLL) that generates a stable CMOS output from an intrinsically low jitter voltage-controlled crystal oscillator. Divided down from the output frequency, the jitter-attenuated internal reference is also available on an output pin. The SCG200 clock generator is able to lock on to any one of four reference frequencies, which are selectable using two input select pins. The device provides what is claimed to be fast acquisition time of about 0.3 seconds with an output independent of the selected reference signal. The miniature timing subsystems reduce design time in a complete single packaged PLL. When used with the company's MSTM Timing Module, the device is essentially a complete packaged telecomm timing system that assures maximum, tight tolerance performance. The MSTM subsystem provides a phase synchronized input, eliminating the need for additional upstream frequency control design elements, engineering and components. The devices are currently available.


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