A Wien-bridge oscillator can produce a very low distortion sine wave at audio frequencies and beyond. It operates by carefully balancing a frequency-selective positive feedback with an equal amount of negative feedback around a high-gain amplifier. The amount of feedback must be continuously adjusted for proper operation. Some textbooks suggest a light bulb or a positive temperature-coefficient resistor for this purpose.
A FET can also do a nice job of controlling the feedback, but the ac voltage across the FET must be kept low to prevent nonlinearities from introducing distortion in the sine-wave output. The trick to overcoming these nonlinearities without sacrificing output amplitude is to use a resistor (R2) in series with the FET (see the figure).
The two resistors (R) and two capacitors (C) comprise the frequency-selective positive feedback network, and set the frequency of oscillation: f = 1/(2πRC). R1, R2, and the FET make up the negative feedback path. For the device to operate properly, R1 must equal approximately 2 × (R2 + RFET), where RFET is the effective resistance of the FET. R2 must be small enough so that R2 + RFET (minimum) is less the 1/2 × R1, or the oscillator won't be able to start. The closer R2 is to 1/2 × R1, the less voltage will be dropped across the FET, and the lower the distortion at the oscillator's output.
The FET's gate threshold voltage controls the oscillator's output amplitude. R4 and C4 set the response of the gain control loop. The circuit given in the figure produces approximately 2.7 V p-p (about 1 V rms) of output at 1 kHz with a measured total harmonic distortion of better than -60 dB (0.1%).
Among the earliest pioneers in developing SSTA technology-was IBM, which now offers the technology through its design-services operation. IBM's Einstat tool was developed from the company's existing Einstimer timing-analysis suite. IBM's ASIC-design teams have used statistical methods in 90-nm ASICs to separate different components of variation. They also use statistical techniques to attribute certain types of variation to specific critical paths, minimizing or removing the need for pessimistic design methods in those paths.
According to Leon Stok, director of electronic design business for IBM's Systems and Technology Group, Einstat now sees two primary applications. "The first major application is the timing signoff. Does this chip meet all my required timing, including noise and power?" Einstat employs path-based analysis to approach timing signoff in great detail.
A second major use of Einstat is in optimization. From the earlier Einstimer tool, Einstat borrows a full incremental engine. "You can make a tiny change in your design and only locally recompute its effects on timing," says Stok. "That enables it to be used in the middle of an optimization. So you can do timing-driven optimization, timing-driven placement, timing-driven logic optimization, timing-driven routing, etc."
A number of hurdles still must be jumped before SSTA sees broad adoption. However, there's little doubt that it will gain favor with designers as they move to 65 nm and begin looking beyond to 45 nm. It's simply a matter of time.
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