An online timing tool crafted by Silicon Labs eases clock-tree design for Internet infrastructure applications. The Clock Tree Expert tool enables fast generation of sophisticated, streamlined clock-tree block diagrams.
Using Silicon Labs’ DSPLL and MultiSynth technologies, the Web-based tool recommends the optimal combination of highly integrated, low-jitter, frequency-flexible clocks and oscillators required to consolidate timing BOM into the smallest number of components.
Designers simply enter the required frequencies, number of clocks, and desired signaling format, and the tool generates a recommended clock tree in moments using the minimum number of timing components. Experienced users can also look into the tool’s “Build Your Own” environment to design clock trees to their exact specifications. Here, the Clock Tree Expert helps find the optimal timing ICs, save and share clock tree designs, generate a BOM list, and order samples.