The Real 64/66 PCI core, when implemented on the company's -6 speed grade Virtex FPGA, provides a fully compliant, yet flexible bus interface for 64-bit, 66-MHz, PCI v2.2 systems. The core gives users the flexibility to build a single-chip design with a standard FPGA. For example, with Real-PCI 64/66 products, the firm has been able to implement a PCI-compliant interface in its new Mx2/PCI product family that also offers other functions, such as DMA, four dual-port FIFOs, and 200,000 gates of a unique design, all on a single IC.The core achieves its PCI v2.2 compliance by using the firm's Smart-IP technology to guarantee critical minimum, maximum and hold timing required for true zero wait-state burst operation at 66 MHz. Compliance is verified through hardware testing, device characterization and regression testing using an internal test bench that simulates more than six million unique combinations of PCI transactions.Virtex FPGAs are manufactured on a 0.22-µm process that meets all timing requirements for 64-bit, 66-MHz performance up to the theoretical maximum throughput of 528 Mbytes/s. The Real 64/66 PCI core is fully verified for the Virtex XCV300-6 BG432 and XCV1000-6 FG680 devices, which offer densities of 300,000 and 1 million system gates, respectively. Designers can choose Virtex device size and package type, customize the PCI feature set, and adapt the design later to future changes in the PCI standard. Both Synopsys and Synplicity support the PCI core in their design flows. Beginning in May, the company is offering a two-day course for customers planning PCI systems. The course offers an introduction to the PCI standard and covers configuration and integration of the Real 64/66 PCI core, as well as system integration, verification and debugging.
Company: XILINX INC.
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