Electronic Design

Add A Synchronous Clock Enable To Any Register

When designing synchronous digital systems with data paths, registers possessing a synchronous clock enable are needed. Use of standard off-the-shelf parts also is required. Unfortunately, few of the standard registers have a clock enable capability. However, by using only an inexpensive, multiplesourced IC and a single resistor, a synchronous clock enable can be added to any register with minimal effects on system timing.

The schematic shows the connections required to add a synchronous —ENABLE input to a positive-edgetriggered register (Fig. 1). The circuit uses one-fourth of a quad 74125-style bus switch. These are available from Texas Instruments (74CBT3125), Quality Semiconductor (QS3125), Pericom (Pl5C3125), IDT (IDT74FST3125), and Fairchild (FST3125). A 74126 style also is available if an active high ENABLE input is required.

The circuit operates as depicted in the timing diagram (Fig. 2). When —ENABLE isn’t asserted, there’s no connection between CLK and CLK_OUT, and the resistor pulls CLK_OUT high. TCO after CLK goes high, —ENABLE is asserted. Then TEN after —ENABLE is asserted, the connection between CLK and CLK_OUT, via the 5-Ω resistance of the pass transistor, is established. When CLK then goes low, it drives CLK_OUT low. When CLK again goes high, CLK_OUT is driven high, and the register is clocked. The propagation delay added by the pass transistor depends solely on the RC time constant, which is less than 500 ps.

The critical timing parameters are the time from the rising edge of the clock to the enable/disable of the connection from CLK to CLK_OUT. The connection must be enabled by TH after CLK goes high to avoid distorting the low time of CLK_OUT. The connection must be disabled by TH after CLK goes high to avoid a second pulse on CLK_OUT. The limiting factor is:


A typical bus switch has a worst case enable/disable time of 5 ns. Assuming a 50% CLK duty cycle and a TCO of 5 ns, a clock rate of up to 50 MHz can be supported.

In actual implementations, there are several caveats. The connection between the bus switch’s output and the CLK input to the register should be as short as possible. Although the CLK_OUT is driven high by CLK, when the switch turns off, it’s only driven by the pull-up resistor. For a long CLK_OUT trace, transmission line effects can cause ringing on the low-to-high edge due to the relatively high impedance of the pull-up resistor. Short traces, such as those required to tie both CLK inputs on a 16-bit-wide device to the same CLK_OUT, aren’t a problem.

Because a bus switch is essentially a controllable wire, it has the effect of changing the loading on the CLK line whenever —ENABLE is asserted. This must be considered when looking at the transmission-line effects on the CLK signal. In some cases, this “problem” can actually be an advantage. When several registers are connected to the same clock signal and only one of the registers is enabled at a time, the clock loading is reduced by 1/N (where N is the number of registers).

The bus switch is powered by 5 V. The effective resistance of the pass transistor goes up well above 5 Ω for input voltages above about 3.5 V. The net effect on the CLK_OUT low-to-high transition is a quick rise to 3.5 V, driven by the CLK signal, followed by a slower rise from 3.5 to 5 V driven by the pull-up resistor. However, even at 3.5 V, the CLK_OUT signal still meets the 5-V TTLlevel requirement of 2.4 V minimum output high voltage.

In 3.3-V systems, the same circuit can be used to switch a 3.3-V clock signals, as long as the CLK_OUT output signal is pulled up to 3.3 V instead of 5 V. In this case, there is no slow low-to-high transition on CLK_OUT. The —ENABLE input can be driven with a 3.3-V TTL-level output if necessary.

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