Paraphrasing Mark Twain, reports of the death of ASICs are greatly exaggerated. Despite the popularity of "ASIC bashing," within some sectors of the microelectronics community, there are still many applications where, due to volume and performance demands, an ASIC is still the best silicon platform for implementing a design.
There is a misconception that all ASICs are alike: high NRE, high complexity, and very difficult and time-consuming to design. But in reality, not all ASICs are created equal. At the low end are low-complexity chips, with lower NRE, high unit cost, and high schedule and cost predictability. These ASICs often can be replaced by FPGAs or structured ASICs. At the high end of the ASIC scale are low-predictability and low-reliability (with regard to achieving first-time silicon success) "science projects." These are the ASICs requiring a high degree of design and management horsepower and are, essentially, custom built.
In the ASIC mid-range are "typical" ASICs, which comprise around 80% to 85% of total ASIC volume. These devices, with modest performance and complexity requirements, comprise the sweet spot for a new ASIC business model that will result in more reliable and cost/schedule-predictable chips costing much less than traditional ASICs. Some parameters that describe mid-range ASICs include random-logic gate counts up to 12 million gates, 10 Mbits or less of memory, power up to 14 W, maximum core speed of 300 MHz (at 0.13 µm), die size up to 16 mm on a side, and a process node from 0.25 to 0.09 µm.
The trick to designing mid-range ASICs is to do them in a "Design Center Unit" environment, using a pool of design talent, a common set of EDA tools and hardware platforms, and a fixed design methodology. While individual chips may need some small variations in the design flow, the overall flow is much the same for all designs. A Design Center Unit, to which chip companies can outsource their designs, offers its customers ASICs that have high predictability and reliability at a cost much lower than that achievable by a traditional ASIC vendor. The Design Center Unit also has the advantage of "design learning," similar to yield learning, where information accumulated from prior designs can enhance the design flow for future designs.
A successful Design Center Unit requires the support of a comprehensive software system. This system should integrate multiple tools into flows; provide a constant design methodology across multiple chips; support designer flexibility to introduce design-dependent variations into the design process; manage machine and tool-license resources; ensure data dependency; and generate useful documentation to gauge design quality, implementation efficiency, and adherence to the predicted schedule.
The successful ASIC business model, along with the Design Center Unit, also needs to include a way to lower manufacturing cost, consistent with achieving chips with high predictability and reliability. This is done with the addition of a manufacturing-chain aggregation service. Supply-chain aggregation lets the aggregator work with many manufacturing vendors—semiconductor foundries, package and assembly, and test—and take advantage of economies of scale and broad aggregator/supply-chain provider experience to minimize manufacturing cost and risk for the customer. Successful aggregation also must support customer input during the different manufacturing operations and 24/7 availability of work-in-progress information.
Successful ASIC design means choosing the right type of ASICs to design (mid-range), developing the ASICs in a Design Center Unit environment, and then implementing the chips via supplychain aggregation. A successful ASIC business model integrates the Design Center Unit and supply-chain aggregation, resulting in less expensive and more reliable and predictable chips for the customer. Underlying the design and manufacturing operations is a software infrastructure that facilitates data logging, gathering, and viewing, along with communication between customer, manufacturingoperations vendors, and design factory/supply-chain aggregation providers.
The system works, and it proves that ASICs are alive and thriving.
