The semiconductor manufacturing community faces a plethora of challenges in the drive to keep Moore's Law alive and kicking (these we'll discuss later). Most IC technologies, such as microprocessors, memories, and logic devices, employ complementary metal-oxide semiconductor (CMOS) technology, which has been around since 1963. As Gordon Moore predicted back in 1965 (with a few revisions since then), the number of semiconductor components (transistors) has doubled roughly every 18 months. This often misquoted and over-quoted prediction became known as "Moore's Law."
We now live in an era where functional requirements, such as mixed-signal RF designs for wireless applications, passive components, and biological functions such as medical delivery systems, are not scaling according to Moore's Law and non-CMOS solutions are used instead.1 But as more technologies merge into system-in-package (SiP) solutions, the integration of CMOS with other technologies, as well as new packaging technologies, will become increasingly important.
Current technology research extends from electron-beam lithography and low-k gate dielectrics to using nature's structures to revitalize Moore's Law and, perhaps, make a quantum leap (literally) ahead.
Today, most large semiconductor manufacturers offer or use 65-nm process technology, with feature sizes as small as 35 nm. To put this number in perspective, it's about 2000 times smaller than the diameter of a human hair. To think we are only two orders of magnitude away from building features at the atomic level (around 100 pm, depending on the element) is mind-boggling.
But can we build features at the atomic scale? It's already being done to a degree in a memory technology named spintronics (Fig. 1). Here, semiconductor manufacturers are researching the use of the quantum spin of electrons and their charge state to indicate a stored memory bit.
In the remainder of this article, we'll explore semiconductor manufacturing issues and trends, plus logic and memory technologies, that will take us out to the year 2020 and beyond.
CURRENT TRENDS There is a grandiose number of major issues1 facing semiconductor manufacturers over the next several years:- Scaling CMOS to 32 nm and below: High channel doping will be required; thus, designers must find ways to reduce gate-induced drain-leakage (GIDL) current and threshold voltages variations while scaling the supply voltage.
- Signal isolation in RF, analog, and mixed-signal design for wireless: As devices scale down while integration increases, signal isolation between the digital and analog portions of the chip becomes a daunting challenge. Also, wireless devices built for low-standby-current applications require high-K gate dielectric materials and metal gate electrodes, which complicates predicting threshold and current mismatches along with pink noise. Increased integration will also challenge the way we think about testing, putting pressure on enhancing mixedsignal co-design and co-verification.
- Lithography (the method of producing patterns on a wafer substrate): Immersion lithography uses ultra-pure water to replace the air gap between the final projection lenses and the wafer. It also increases the resolution of the pattern etching process. Immersion lithography, along with more refractive lenses, will be needed for 32-nm process technology. 32 nm will be the approximate limit that can be reached using a 193-nm wavelength laser. Breaching the 193-nm wavelength limit used in optical lithography requires a new technology. So far, those entering the fray include extreme ultraviolet lithography (EUVL), maskless lithography, and imprint technology, with EUVL being the likely candidate to take us down to 16 nm and below.
- Interconnect: As feature sizes shrink, signal propagation delay and power consumption must be minimized using a low dielectric constant (low-K) material of around 2.0. The challenge after that will be to make a non-brittle, porous dielectric to reduce the dielectric constant to around 1.4 or less.
- 450-mm wafers: The move to 450-mm wafers (from 300 mm) will roughly double the number of dies per wafer. Expectations for this technology's arrival are around the year 2012. If this date is to be met, though, the industry must significantly step up research efforts and adopt numerous standards in the areas of wafers, metrology, and processing equipment.
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On-chip parallelism: Servers and even personal computers have taken advantage of parallel processors for years. We've also seen increases in onchip parallelism over the years, with such things as pipelining, math coprocessors, and multithreading. Today, though, true independently operating multicores are all the rage, but they do provide their own set of challenges.
According to Intel CTO and Senior Fellow Justin Rattner, when multiple independent cores and multithreading are combined, we lack the quantitative tools to deal with sophisticated scalable on-die fabrics and must provide better explicit thread support. These issues will be overcome using architecturealgorithm co-design with new instructions and cache design improvements. - Design For Manufacturing (DFM): Designers will need to pay increasing attention to DFM (See "10 Semiconductor Manufacturing DFM Rules Every Designer Should Follow," p. 47).
Carbon nanotubes: By its very nature, carbon-nanotube (CNT) technology is ideally suited to create electric circuits at the nano scale. CNTs are a form of carbon that take on cylindrical shapes (Fig. 2) and exhibit outstanding bond strength (stronger than bonding in diamonds) and unique electrical properties, such as extremely high current densities.
CNTs have many applications outside of electric circuits, but to date, researchers haven't found a reliable method to arrange them into a complete circuit that's manufacturable on a large scale. CNTs naturally tend to align themselves into intersecting hexagons that form into tubes, which doesn't lend itself to forming complex semiconductor logic. However, the predictable patterning of memory structures in crosspoint formations may be a more ideal starting point for the use of CNTs. Researchers are looking for ways to create more complex CNT circuits by placing one end of the nanotube down and growing the rest into desired patterns using a catalyst in combination with a chemical vapor deposition process. That's because CNTs tend to grow along field lines from negative to positive polarity.
The last major hurdle researchers face in using CNTs in electric circuits involves controlling the actual type of CNT produced, from metallic, semiconducting, single-walled, and multiwalled. Currently, there's no reliable way to do this. So, researchers are turning to chemical engineering for the answers.
Superconducting circuits: Since Heike Kamerlingh Onnes discovered the phenomena of zero resistance in certain materials in 1911, other elements and compounds have been found to become superconducting at temperatures ranging from less than one degree K to 120 K.
In addition to being perfect conductors, the interiors of superconductors have zero magnetic field (the Meissner effect). Furthermore, another key property is that the magnetic penetration depth of superconductors is frequency-independent, unlike normal metals.
Superconductors also offer the following additional benefits over traditional metals and semiconductor devices:
- Very low operating power
- Zero dc electrical resistance
- Orders of magnitude lower RF resistance
- Virtually lossless and dispersionless transmission lines
- Ultra-low power dissipation.
With these advantages, it's easy to understand why superconductors are ideal for high-speed RF and mixed-signal devices, such as data converters, phaselocked loops (PLLs), memories, and signal-processing applications.
Hypres is using superconducting microelectronic (SME) technology to create the industry's first all-digital transceiver by moving electrons right at the antenna—a process known as direct digitization. Signals are then processed on receive and transmit at ultra-high speed and accuracy using SME, thereby making the transceiver all-digital.
"When applied to wireless communications, 'Digital RF' offers profound improvements in wireless operating efficiency, data-signal strength and speed, power conservation, and equipment cost reduction," says Dick Hitt, CEO of Hypres.
The primary disadvantage to using superconducting materials is the requirement to cool them to cryogenic temperatures. (The Hypres SME technology becomes superconductive at 4 K.) However, advances in refrigerator technologies allow for much smaller refrigerators, with some being around the size of a breadbox or thermos.
Molecule cascade: If you like setting up dominos and knocking them over, you'll find IBM's new molecular cascade technology interesting. It employs the same domino-toppling effect.
When several carbon monoxide (CO) molecules are properly aligned, moving a specific CO molecule initiates a cascade of molecular movements. Scientists have combined these molecules to form very small logical AND and OR functions, data storage, and interconnect so they actually function as mini circuits (Fig. 3). In fact, these circuits are 260,000 times smaller than today's smallest semiconductor technology.
To date, scientists have built circuitry as complex as a three-input sorter that occupies a mere 12 by 17 nm. To give you an idea of scale, you could fit about 190 billion of these sorters on top of a standard pencil-top eraser (about 7 mm in diameter), give or take a few billion.
The basic idea is to arrange CO molecules on a copper surface in a metastable configuration that, under certain conditions, will cascade into a lower energy configuration similar to toppling dominos. By their nature, CO molecules exhibit weak repulsion when placed one lattice spacing apart and are monostable in this configuration.
If you think of an un-toppled set of dominos representing a logic zero and a toppled set as logic one, the same concept can be applied to a molecular cascade. IBM researchers Heinrich and Lutz found that if the intersections of such cascades were cleverly designed, logical ANDs and ORs could be created.
Heinrich and Lutz designed molecular arrangements that acted as crossovers (allowing two cascade paths to cross over each other) and fanouts (splitting one cascade into two or more paths).
One issue researchers must resolve before these cascades can be used as circuit elements is how to "reset," so they can perform their function more than once. Yet they do believe it's possible.
3D trigate transistor: At the 2006 VLSI Symposium, Intel unveiled plans to develop a three-dimensional logic transistor called a FinFET (Fig. 4). With production anticipated by 2015, the devices promise improvements in standby current and reductions in leakage current that's plagued the industry for several years. Another promise expected from FinFETs is the potential scaling to the 10-to 15-nm range, assuming that manufacturing problems related to pitch (the space between transistors) can be overcome and 3D etching perfected.
PACKAGING TRENDS The semiconductor packaging industry faces its own set of challenges while transitioning to newer, more environmentally friendly materials and new standards introduced in the RoHS initiative. For instance, packaging companies must deal with increasing device complexity and keeping pricing down as material costs escalate. To combat these issues, the packaging industry has come up with some interesting new technologies:
Redistributive Chip Packaging (RCP): Flip-chip was an important packaging breakthrough that eliminated wire bonding and made ball-grid array (BGA) possible. Using flip-chip, a die is connected face-down to a board or substrate using the conductive bumps (balls) in a BGA.
Freescale recently introduced RCP technology, which takes flip-chip a step further by eliminating package substrates altogether. This increases interconnectivity in a way that can't be accomplished using today's organic substrates.
Organic substrates limit the thinness of the routing traces that connect wire bonds to solder-balls, and thus limit I/O density. RCP lets the bond fingers be pulled into the die, creating a smaller package with higher I/O density.
RCP packaging reduces the size of high-pitch packages by up to 50%. By eliminating the substrate and enabling large area batch processing, RCP lowers packaging costs. RCP allows for high-density pad array designs and provides significant design flexibility with improved noise, power distribution, and thermal characteristics.
Quad flat no-lead (QFN): QFNs are leadless, near-chip-scale packages (CSPs) that have become popular due to their compact size, reduced weight, and excellent thermal and electrical characteristics. With QFNs, die pads are exposed (Fig. 6), which brings about efficient heat dissipation and high power capability. Advanced Interconnect Technologies offers an ultra-thin QFN package with a 0.60-mm-thick package profile. The lower profile allows for board-space reduction, package efficiency in the zdirection, shorter electrical paths for increased power yield, and overall system weight reduction or a larger die thickness.
References
1. "International technology roadmap for semiconductors: executive summary," 2005 ITRS; PDF; hundreds of authors contributed to this document.
Drill Deeper at www.electronicdesign.com For more, see "New And Emerging Memory Technologies," Drill Deeper 13494, and "An On-Chip Parallelism Frenzy," Drill Deeper 13495.