Electronic Design

Breaking News: Second-Generation Reduced-Latency DRAM

First samples of the second-generation Reduced-Latency DRAM are being released by Micron Technology Inc. These 288-Mbit devices operate at 400 MHz and use double-data-rate signaling for data transfers. The RLDRAM II chips also offer fast random access with extremely high bandwidth and high density. The memories can achieve a peak bandwidth of 28.8 Gbits/s using a 36-bit interface and a 400-MHz system clock. The chips have a low latency and a random cycle time (tRC) of 20 ns, providing optimum bus-utilization efficiencies. Also included are on-die termination, multiplexed or nonmultiplexed addressing, on-chip delay-locked loop, common or separate I/O, programmable output impedance, and a 1.8-V core. The RLDRAM II chips come in 11- by 18.5-mm, 144-ball FBGA packages. See www.micron.com for details.

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