Electronic Design

Chipping Away At Design West 2012

One thing that always shows up at the Embedded Systems Conference/Design West is chips and lots of them. Everthing from microcontrollers to microprocessors to FPGAs. Here we take a look at the two ends of this spectrum.

Also at the show were dev kits and demos for newly released chips like Texas Instrument's 16-bit MSP430FR58xx Wolverine series. The Wolverine has unified FRAM storage subsystem for code and data (see FRAM Microcontroller Targets Low Power Applications).

And now onto the other details.

Microchip PIC16F178x

Microchip added the PIC16F(LF)178X (Fig. 1) to its mid-range PIC microcontroller family. The 32 MHz chips incorporate a 12-bit ADC and an 8-bit DAC along with op amps and high speed, 50 ns comparators. The ADC can be use for mTouch capacitive sensing support.


Figure 1. Microchip's PIC16F178x incorporates advanced analog peripheral integration

The chips have 256 bytes of EEPROM and up to 512 bytes of RAM. Programs can be as large as 14 Kbytes. Serial interface support includes I 2C, SPI and EUSART.

The new Programmable Switch-Mode Controllers (PSMCs) are based on 16-bit Pulse-Width Modulation (PWM) counters that run up to 64 MHz. They incorporate additional timing capabilities.

The LF version implements Microchip's eXtreme Low Power Technology. They use 32 µA/MHz in active mode and only 50 nA in sleep mode. The PIC16F supports an internal 32 MHz oscillator and is available in 28- and 40-pin packages.

STmicroelectronics STM32 F0

STmicroelectronics' STM32 F0 (Fig. 2) is based on Arm's Cortex-M0 architecture and is priced under $1. It can be an HDMI Consumer Electronics Control (CEC) device.


Figure 2. STM32 F0 supports the HDMI Consumer Electronics Control (CEC) device interface.

The 48 MHz STM32 F0 Series has up to 128 Kbytes flash and 20 Kbytes SRAM. Some chips in the family have RAM parity support. There is also a DMA-supported CRC integrity check of flash memory. These features are required for Class B-ready, safety-related applications. Dual watchdog timers are provided as well.

The Cortex-M0 is at the low end of the power and performance spectrum but it delivers 1.6 CoreMarks/MHz. It is very power efficient using only 5µA in stop mode and 2µA in standby mode. The analog peripheral set includes a 12-bit, 1 Msample/s ADC as well as a 12-bit DAC and a pair of comparators. These peripherals use a separate power supply. Capacitive touch support can handle buttons, sliders and wheels.

The digital peripherals include serial ports with IrDA support, a 1 Mbit/s I2C interface plus SPI. The 32-bit timers work with up to 17 capture-compare pins. The timers support PWM and there is separate motor control subsystem for permanent magnet synchronous motors (PMSM).

Xilinx - FPGA Development Tools

Xilinx is now delivering its latest Series 7 FPGAs (see Xilinx Unifies FPGA Line) and FPGAs with hard Cortex-A9 cores (see FPGA Packs In Dual Cortex-A9 Micro). These are now available in development boards like the Virtex-7 VC707 (Fig. 3).


Figure 3. The VC707 supports Xilinx's latest Virtex-7. It can plug into a x8 PCI Express slot.

These boards are part of Xilinx's targeted design platforms that have been successful in the past addressing application areas such as video processing. The new Zynq-7000 EPP (Extensible Processing Platform) is getting a boost with its software development tools to address the dual Cortex-A9 cores.

Renesas RX62G

Renesas Electronics was talking about its new RX62G (Fig. 4). It is designed for applications that need high-accuracy and effective digital control such as motor control and digital power supplies. The 32-bit family delivers 165 Dhrystone MIPS (DMIPS) performance at 100 MHz and features high-resolution timers with 312.5 picosecond resolution.


Figure 4. Renesas RX62G features high-resolution timers with 312.5 picosecond resolution.

The chips feature a single precision, floating point unit (FPU) and DSP functionality. It has a pair of 12-bit ADCs and an additional 20-channel, 10-bit ADC with a minimum conversion time of 1 µs. The three ADCs can be timer triggered to sample three phase inputs simultaneously. The 16-bit PWM timer and MTU3 multifunction timer is designed for motor control applications. A single RX62G can control up to three 3-phase motors simultaneously. The RX62G series is pin-compatible with the RX62T series

Freescale Kinetis L

Freescale's Kinetis L series (Fig. 5) extends the product family into the low cost, low power arena using Arm’s Cortex-MO+ architecture that improves upon the Cortex-M0 architecture. The both use the same instruction set but the new architecture adds features like a trace buffer for debugging. It also has a faster, single-cycle I/O interface.


Figure 5. Freescale Kinetis L is based on Arm's new Cortex-M0+ architecture.

The Kinetis L uses the same Thumb-based instruction set as the Cortex-M0. This subset of the instruction sets is implemented on the higher-end Arm architectures, including the other Kinetis Cortex-M4 chips.

The minimum Cortex-M0+ footprint is only 12k gates. It employs a two-stage pipeline with a two-cycle branch turnaround. The instruction fetch has been optimized to minimize flash memory access and to reduce power requirements. It is definitely going to be a challenge to 8- or 16-bit microcontrollers.

The KL0x series is pin-compatible with Freescale's own 8-bit S08 line. The KL1x series is pin-compatible with the Cortex-M4 Kinetis series.

Texas Instruments C66xx Keystone

Texas Instruments has been showing off two families of its C66xx Keystone architecture. The high end, 28nm Keystone II targets base stations and incorporates accelerators for this application area. At this show the C6654, C6655 and C6657 took center stage (Fig. 6). These 40nm devices target mobile devices were cost and power are key design factors.


Figure 6. Texas Instruments TMDSEVM6657 evaluation module (EVM) lets designers get started with the C665x platform.

The TMS320C665x DSPs come in a compact 21mm by 21mm by 2.9mm package. They are available in versions that handle -55C for applications like automotive and avionics. The Serial RapidIO links can be used to connect the DSPs to other processors in a fabric such as a radar system.

The chips deliver a fixed point score of 80 GMACs/core and floating point score of 50 GFLOPs/core. The single core, 850 MHz C6654 uses 2W while the 1 GHz, single core C6655 uses 2.5W. The 1 GHz, dual core C6657 uses 3.5W. These chips skip the hardware accelerators designed for base stations but retain the ones for telephony.


TAGS: Freescale
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