Clock-Generator IP Blocks Let ASICs Deliver Precision Timing

Oct. 27, 2005

Designers can use a family of precision phase-locked loops (PLLs) available as hard macrocells to deliver system clocks, perform built-in frequency margin testing, and deliver stable clocks for serializer/deseriaizer and video applications. Developed

Dave Bursky

Developed by True Circuits, these blocks of intellectual-property (IP) macros provide frequency modulation and very high frequency resolution with over 16 bits of control. The TCI-TN90G-HRMPLL macro offers a divided reference frequency range of 6.235 to 400 MHz with reference divider values ranging from 1 to 64.

The macro's period jitter (peak-to-peak) is ±2.5% of the output cycle (worst case), while input-to-output jitter is ±1.25% of the divided reference cycle. It consumes just 7 mA when running at 400 MHz and has a lock time of 500 divided reference cycles. The company's proprietary LockNow! technology can considerably shorten the lock time.

The initial PLLs will be available in the first quarter of 2006. They will target TSMC's, UMC's, and Chartered Semiconductor's 250- to 65-nm processes. They're supplied as GDS II and LVS Spice netlists along with behavioral and synthesis models, library exchange format files, and extensive documentation. Contact the company for licensing fees.

True Circuits Inc.
www.truecircuits.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.