Standard SDRAM can operate in a page mode at speeds of 100 to 133 MHz. This should not be confused with random access, which ranges from 25 to 30 MHz in commodity DRAM. Page-mode operation can be exploited only when large chunks of data can be organized on the same page. Recent naming conventions for SDRAM such as PC-100 and PC-133 refer to the page-mode clock frequency, rather than the random-access or random-cycle time.
When several words of data from a single page are required, the page mode can be employed to achieve higher data bandwidths. The figure shows the waveforms for an SDRAM page mode where three successive words of data are required. The operation is identical to the single word read in Figure 1—up to the first read command. A wordline is raised and a full row of sense amplifiers is activated to sense a full page of data. After an appropriate delay, a first read command accesses a portion of the page and sends data to the output. Following this command, instead of issuing a precharge command, another read command with a different column address is issued. This can continue until the entire page is read out, providing a continuous burst of data at the full clock speed. Three reads are performed in this example, requiring a total of seven clock cycles. If simple single-read cycles would have been employed, 15 clock cycles would have been necessary.
Clearly, a page mode brings significant benefits to applications where data accesses follow predictable patterns and can be localized within page boundaries. A graphics frame buffer is one such example. But many applications, such as cache memory or networking switches, cannot benefit from a page mode. For these applications, it would be better to re-architect the core DRAM array and even eliminate the page mode to improve random-access cycle time.