CPLD Family Boasts Lightning Speed And Low Power Dissipation

With lightening-fast pin-to-pin delay times and operating frequencies, plus low power dissipation, the 256-macrocell ispMACH 4256 and 512-macrocell ispMACH 4512 are designed to deliver advanced glue logic, state machine, decoder, bridging, power-up, and signal handshaking functions to high-performance computing, communications and industrial systems. These first two members of the ispMACH 4000 SuperFAST family of complex programmable logic devices (CPLDs) are available for operation at 2.5V or 1.8V, with I/O operation supported at 3V, 2.5V and 1.8V. The 4256 CPLDs have 3.0-ns pin-to-pin and clock-to-output delays, 2.0-ns set-up time, and a 300-MHz operating frequency, reportedly 40% faster than competitive devices. The equivalent specs for 4512 CPLDs are 3.5 ns, 2.4 ns and 256 MHz. Other specs and features for the two devices include low static current (1 to 3.5 mA for 1.8V and 9 to 11 mA for 2.5V devices), four global clocks, 36 inputs per logic block, IEEE 1532 in-system programmability, hot socket capability, 3.3V PCI compatibility, and programmable output slew rate. Manufactured using a 0.18-micron E2CMOS non-volatile process, the ispMACH 4256 CPLDs are projected to cost as little as $6.50 each when large volumes become available in the second half of 2002. IspMACH 4512s will be priced from $15. Both devices are available in 176-pin TQFPs and 256-ball fpBGAs. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000.