Electronic Design

Data-Flow Control Memories Handle Many Data Streams

By integrating memory queues, multiplexers, and control logic, these data-flow memories manage data movement in digital communication/network systems.

In networking and data-communications systems, data streams constantly move from subsystem to subsystem. To avoid data starvation or data overflow, most systems use large memory queues, multiplexers, and control logic to manage the data movement. Integrated Device Technology has combined all of those functions into a novel device called a data-flow controller. So in one chip, designers have all of the resources needed to simplify the design of the data subsystem.

There are actually three architecture variations of the flow-control memories: the IDT72T552xx, 72T512xx, and 72T515xx. Each has a different memory queue organization. Furthermore, each variation comes in several memory capacities. For example, the IDT72T552xx has three versions: the '248, '258, and '268. All contain four queues, each with its own 10-bit wide data ports. Every queue buffer is either 8 kwords by 40 bits, 16 kwords by 40 bits, or 32 kwords by 40 bits (the '248, '258, and '268, respectively).

In the multiplexing mode, all four queues' internal ports connect to a multiplexer. The multiplexer links to an external data port that can be user-configured to transfer data as 10-, 20-, or 40-bit wide words. The chip can also operate in a demultiplexing mode, accepting 10-, 20-, or 40-bit wide words and delivering four 10-bit wide data streams.

Known as a quad-multiplexer/demultiplexer chip, the memory employs a user-selectable single- or double-data-rate (DDR) signaling interface to handle the high-speed data streams, which can clock into the chips at rates of up to 200 MHz (16-Gbit/s total bandwidth with DDR signalling). Each port has its own independent clock domain, permitting the system to selectively control each queue port and the master data port.

The IDT72T512xx series has four unidirectional queues with similar memory capacities as the '72T552xx series. It also incorporates multiplexers on the input and output so that the 10-, 20-, or 40-bit data words presented at the data-input port can be switched to any of the four queues, and any of the four queue outputs can be switched to the data-output port. That allows the chips to deliver 10-, 20-, or 40-bit data words, suiting bus-width matching applications.

The third variation, the IDT72T515xx series, has three members that offer total memory capacities of 512 kbits, 1.2 Mbits, and 2.4 Mbits (the 72T51536, '546, and '556, respectively). These devices feature a 36-bit datapath and provide up to 32 FIFO queues. The FIFO queues' depth can be individually configured upon reset in blocks of 256 words drawn from the memory pool.

The IDT72T552xx and 72T512xx come in 324-contact BGA packages. The IDT72-T515xx flow-control chips come in 256-contact plastic BGAs. Prices start at $53.53 each in 10,000-unit lots for the 72T55248 and $42.50 for the 72T51248. Prices for the IDT72T515xx start at $32.13 each in similar quantities.

See associated figure

Integrated Device Technology Inc.
(800) 345-7015

See block diagrams of the three architectures.

The novel one-chip data-flow controller created by Integrated Device Technology comes in three architecture variations: the multi-queue DDR flow-control memory with four fixed queues (a); the quadmax DDR flow-control memory with mux/demux/broadcast features ; (b)and the multi-queue flow-control device with up to 32 queues (c). Model numbers are the IDT72T512xx, IDT72T552xx, and IDT72T515xx, respectively.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.