The wheels of innovation are spinning at a breakneck pace in the world of NAND flash memories. With storage capacities hitting 16 Gbits, these memories offer the densest storage of any solid-state memory technology. Look fast, though, because further advances in cell structures, circuit architecture, and process technology will soon leave that number in the dust, raising the bar for NAND flash storage capacity and performance.
Today, NAND flash memories are in high demand for image storage in both digital still cameras and solid-state MPEG-4 video cameras. They're also widely used for music and video storage in the latest media players, such as the Apple iPod Nano and the SanDisk Sansa family. Emerging applications portend huge demand for internal and removable storage for image-, video-, and music-capable cell phones, too.
TWO TYPES OF NAND
NAND flash devices are available in two main implementations: single-bit-per-cell (single-level cell, or SLC) and two-bit-per-cell storage. Two different schemes are used to store the latter. The multilevel cell (MLC) uses multiple charge levels. The other scheme, called MirrorBit by Spansion, stores two separate charges, one at each end of the transistor gate (Fig. 1).
Samsung and Toshiba—using MLC schemes—offer the highest-capacity monolithic NAND flash chips available today, at 16 and 8 Gbits, respectively. When the MLC cells aren't as stable as desired, the MLC array can be turned into SLC-based devices during manufacturing by disabling the circuits used to create and sense the multilevel charge values.
From an external viewpoint, the SLC and MLC devices have similar interfaces and control signals. Yet the internal differences between the two cell structures make the technology selection an important part of the overall design decision (see "Paying For Double Density," p. 53).
The SLC memory cells use a single charge threshold to decide whether the cell stores a "1" or "0," which makes value sensing a relatively straightforward task(s). But to ensure data integrity, SLC memories typically employ a single-bit error detection and correction (EDC) scheme that can repair single-bit failures in each data byte.
MCL memory cells, pioneered by Intel, take a different tack. They "divide" the stored charge into four ranges by setting up three charge threshold division points, so that the four ranges can be coded into two bits (Fig. 2b). Each charge state has a range span that's about one-quarter the size of an SLC cell.
The smaller charge per bit could make each bit in the cell more sensitive to upsets, which may change the bit values. As a result, to correct multibit errors, manufacturers of MLC NAND chips often embed EDC schemes that are more complex than those used in SLC NAND devices. Such schemes add to the circuitry overhead while slowing down memory-access speeds and data-transfer rates.
ON THE MARKET
Intel's StrataFlash MLC scheme and Spansion's MirrorBit scheme deliver two bits per cell. But the memory architectures offered by both companies are NORbased rather than NAND-based. NOR-based flash memories offer full random access to the data, which also means more overhead circuitry.
The extra circuits limit memory capacity to about one-sixteenth that of NAND flash chips for devices with roughly the same chip size. Intel and Spansion are sampling 1-Gbit dualbit/cell devices, while Samsung and Toshiba are sampling 16-and 8-Gbit chips, respectively.
Capacity is the main driving force in the market. Many flash vendors use multichip packaging to further double or quadruple their package capacity. For example, Toshiba is sampling a 16-Gbit solution by assembling two 8-Gbit chips in a package. It can be delivered many months before a monolithic version might be producible.
By making the package pinout compatible with the next-generation device, the multichip solution can be replaced with a future, more cost-effective monolithic chip. At the same time, the next double-density multichip packaged solution using the new monolithic device can be released, thus paving a long-term upgrade path.
The slight differences between each vendor's NAND flash chips (internal architecture and timing/control differences) make it nearly impossible to get a direct replacement for another vendor's chip. At last month's Intel Developer Forum, Intel proposed developing a standard interface for NAND flash devices to eliminate the need to craft custom controllers. It's too early to tell if this proposal will gain any traction with the NAND flash manufacturers.
To hide the differences between NAND flash vendors, companies such as M-Systems, SanDisk, and Silicon Systems designed their own memory controllers with a generic host interface. These controllers can be software-configured to a particular flash memory's characteristics. Or, they might contain a lookup table that lets the company select from a number of known devices.
Such controllers not only contain the basic memory-control interface, they also often include extra EDC capability to ensure data integrity. In addition, MLC devices are usually specified with a guarantee of 10,000 write operations per bit before failing due to wearout (a buildup of charge that raises the transistor threshold so its ON and OFF states are nearly indistinguishable). SLC chips are a bit more durable and often are specified with a 100,000-cycle write capability.
To extend MLC and SLC memory life, the memory subsystem controllers and usually the host-based, operating-system software will add a capability called wear leveling. The wear-leveling scheme allows all portions of the chip or chips in the flash-memory array to be written to about the same number of times. This minimizes the chance of early wearout by preventing the same memory location from being written over and over again. Thus, a multigigabit chip with a native 10,000-cycle life typically can provide million-cycle endurance.
The controllers also can implement a multibank read or write to improve memory system performance. By splitting the data between two or more banks of memory, the controller can speed the apparent read or write operations by switching banks once an operation is initiated. The native 3-to 6-Mbyte/s programming speed then can usually be doubled at the subsystem level.
THE LATEST PROCESS TECHNOLOGY
Today's highest-capacity NAND flash devices leverage advanced process technologies. For instance, Samsung's 16-Gbit NAND flash memory employs 50-nm minimum features, while Toshiba's 8-Gbit chip is manufactured with 70-nm process rules. But smaller feature sizes won't be enough to push densities beyond 16 Gbits for NAND flash and perhaps 4 Gbits for MLC or MirrorBit NOR devices.
In addition to the current vendors of NAND flash memories, Intel and Micron have inked a deal to jointly develop and manufacture NAND flash memory by forming a new company, IM Flash Technologies. The new company combines Micron's expertise in developing NAND technology and operating highly efficient manufacturing facilities with Intel's multilevel cell technology and history of innovation in the flash business. Initial production from the company will start in the first half of this year using existing facilities in Boise, Idaho, and Manassas, Va.
Micron has had SLC NAND flash devices in development, and it has already released 2-Gbit devices (256-Mword by 8-bit and 128-Mword by 16-bit). By using its multichip packaging capabilities, it also offers 4- and 8-Gbit solutions in 48-lead thin small-outline packages. The MLC devices are expected later this year and will support customers such as Apple Computer, which prepaid each company $250 million to ensure a supply of NAND flash devices for its iPod media players.
Researchers at Saifun Semiconductors and Macronix jointly disclosed a 4-bitper-cell technology at the February IEEE International Solid State Circuits Conference (ISSCC). Based on the nitrided ROM (NROM) technology that formed the basis for the MirrorBit memory cells, the scheme uses localized charge trapping in an oxide-nitride-oxide gate dielectric layer. When a standard NROM cell is operated in 4-bit mode, two bits of data are stored in each of its two separated storage areas (Fig. 3). Like the MLC cells, the charge in each of the two storage areas is divided into four threshold levels.
Pushing gate lengths down to just 20 nm, researchers at Taiwan Semiconductor Manufacturing Corp. and National Chial-Tung University detailed a high-performance FinFET silicon-oxide-nitride-oxide-silicon (SONOS) structure. It can incorporate multilevel storage to further improve storage capacity.
Initial results presented at the IEEE International Electron Devices Meeting (IEDM), held Dec. 5-7, 2005 in Washington, D.C., show a large threshold voltage window of about 2 V for two-level (single-bit storage) operation and about 4.4 V for multilevel operation (two bits/cell). The experimental memory array also has a high program and erase speed—just 10 µs for programming and 1 ms for erase.
To improve the reliability of MLC memories, research between STMicroelectronics and Hynix Semiconductor led to an error checking and correction (ECC) scheme based on a five-error BCH code over a 2102-byte data field with 10 parity bytes (Fig. 4). Presented at ISSCC and implemented on a 4-Gbit MLC NAND flash memory, the ECC approach delivers two major benefits— it's fast, and it adds only about 1% to the chip area.
Up to 36-Mbyte/s read speeds can be achieved with an external controller that uses a 16-bit wide interface. The internal ECC logic runs at over 25 MHz. If no error is detected, the ECC overhead time for program and read operations is only 500 ns. A 40-bit basis corrector is employed if two to five errors are detected. It adds 250 ms, while one with a 16-bit basis manages the more likely single-bit error in just 34 ms.
The ISSCC also saw Toshiba and SanDisk deliver details of their next-generation 8-Gbit MLC NAND flash, which can deliver a programming throughput of 10 Mbytes/s. Based on 56-nm design rules instead of the first-generation device's 70-nm rules, the new chip will program almost twice as fast as previous MLC chips, keeping pace with many of the SLC memories.
These developments illustrate how plenty of room is left for growth in the NAND flash market, as well as in the multibit/cell NOR flash markets. In fact, we've seen demonstrations of other technologies that promise still higher capacities without a wearout mechanism, such as magne-to-resistive memories, phase-change memories, and even carbon nanotube memory structures. However, don't hold your breath for gigabit capacities in the near term. It will take at least several more years before demonstrations occur at these density levels.
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