Electronic Design

Designing With Structured ASICs

Sponsored by: ALTERA CORP.

What makes the structured ASIC cost effective?

It's a matter of per-unit cost, including all of the associated overhead, in volume. Many factors must be added up to determine the final per-chip cost, such as the quantity needed, the cost of the mask set, the design and verification overhead, and the size of the chip. Structured ASICs provide a "middle ground" between field-programmable gate arrays (FPGAs) and solutions based on full standard cells. When you examine all these factors together, you can accurately estimate when it's more economical to use a structured solution versus an FPGA or full cell-based approach.

What are the tradeoffs when committing to structured ASIC?

All the basic building blocks are premanufactured, and wafers containing the uncommitted logic can be kept at the ready. As a result, time-to-market from completed physical design for structured ASICs is two to four weeks compared to the two to three months for a cell-based alternative. Design verification time also is often shorter since the structured ASIC vendor already has preverified the preintegrated functions. But the starting chip is somewhat generic before the design is started, so its size may be larger and its performance may be slightly less than what can be achieved with a cell-based ASIC. However, structured-ASIC areas are significantly smaller than equivalent-complexity FPGAs. Also, the structured ASICs' performance often will be much higher than what's possible with an FPGA.

Click here to download the PDF version of this entire article.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.