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Electronic Design

Digital Current-Mode Control Challenges Analog Counterparts

Switch-mode power supplies can use digital current-mode techniques for protection against peak currents, magnetic field "ratcheting," and input-voltage variations.

Digital control of switch-mode power supplies (SMPSs) is becoming practical thanks to the evolution of low-cost, high-performance devices with peripherals designed for power-conversion applications. Also, current-mode control is challenging voltage-mode techniques for SMPS digital designs. Combining digital control with current-mode topologies can bring higher performance than combinations of analog or voltage-mode approaches.

Early SMPS designs used voltage-mode control. A ramp generator drives one input of a voltage comparator, and the error signal from the error amplifier/loop filter drives the other input (Fig. 1). The result is a pulse-width-modulation (PWM) pulse based on the voltage error signal. This circuit had two basic limitations, though. There's no inherent current limiting to protect circuit components, and it responds slowly to input and output transients.

As SMPS designs matured, designers moved to current-mode control (Fig. 2). Here, a current-feedback signal driven by the inductor current replaces the ramp generator. The result is a system in which the error signal directly controls the peak current in the inductor, eliminating potential circuit failures due to excessive current conditions. Because current-mode control manages the inductor current, the pole or delay due to the inductor is effectively removed from the control loop, improving the system's transient response.

An important issue with most analog current-mode PWM controllers is that they can only measure peak current. Designers really need the ability to measure average current, because the average current is integrated with the output capacitor to produce the desired output voltage.

Usually, designers can approximate the average current as half the peak current. For duty cycles less than 50%, there's enough time for the inductor current to decay to zero before the start of the next PWM cycle. As long as the inductor current reaches zero by the end of the PWM cycle, the average current will equal half the peak inductor current (Fig. 3).

This design generally works well. But when the duty cycle is greater than 50%, some issues arise. Primarily, the average current is no longer approximately equal to half the peak current (Fig. 4). As the PWM duty cycle rises above 50%, the average current becomes increasingly larger than what's expected by measuring peak current.

The resultant output voltage will be higher than desired, and it will continue to rise until the slower voltage-control loop readjusts the current set point. The output voltage will then drop below the desired level. This process, known as subcycle oscillation, will repeat.

To fix this current-mode instability, analog current-mode controllers employ slope compensation that adds a falling-edge sawtooth voltage to the current threshold generated by the voltage-error amplifier (Fig. 5). This creates a new current threshold for the current-limit comparator, which more closely tracks the average inductor current.

A digital approach to current-mode control overcomes many of the limitations of digital voltage-mode PWM controllers. Digital current-mode control protects transistors against peak currents, eliminates magnetic-field "ratcheting" in the magnetic components, rejects input-voltage variations, and simplifies control-loop compensation.

Current-mode control also uses the error voltage to control the maximum inductor current, which turns the inductor into a voltage-controlled current source. As a current source, the inductor no longer generates a pole in the loop's frequency response. This changes the loop from unconditionally unstable to conditionally stable, simplifying loop-filter design.

Digital signal controllers (DSCs) can perform digital current-mode control with the proper on-chip peripherals. However, many lack analog comparators and analog-to-digital converters (ADCs) able to measure inductor current at the appropriate points during the PWM cycle. Without some means to accurately measure current at the desired point, the DSC would have to constantly measure the inductor current with the ADC during the PWM cycle to "catch the moment" when the inductor current reaches the desired level.

Achieving 12-bit resolution demands up to 2048 ADC current conversions per PWM pulse. The required ADC sample rate would be 1 billion samples/s. In addition, sufficient processing power is needed to collect these 1 billion conversions, compare each to the error signal, and shut down the PWM output when reaching the desired current. Conservatively, this means designers need a processor capable of a billion instructions per second (BIPS). As such, it's not cost-effective.

DSCs with the appropriate peripherals can implement current-mode control in digital SMPSs. Many possible methods exist for performing current-mode control when implementing an SMPS design with a DSC. In the digital current-mode approach, the key is use of a DSC with an on-chip PWM peripheral that works in the same way as a standalone current-mode PWM generator (Fig. 6).

Two mixed-signal components, a voltage comparator and a digital-to-analog converter (DAC), are added to a normal, timer-based PWM peripheral (Fig. 7). The voltage comparator supplies a shutdown signal to the PWM module, which is gated together with the output of the duty-cycle counter. When the duty-cycle counter reaches zero, the comparator output can drive the PWM output to zero.

The DAC receives its input from the DSC and generates a reference signal into the comparator. When the system is integrated into a digital SMPS, the counters in the PWM module start the PWM pulse, the DAC generates a voltage at the inverting input to the comparator representing the inductor's desired current, and the current feedback feeds into the comparator's non-inverting input.

As the current builds in the inductor, the duty-cycle counter continues to count up. If the inductor current reaches the desired level first, the comparator terminates the pulse and the inductor begins to discharge into the output capacitors. If the PWM counter reaches the specified duty-cycle value first, it terminates the PWM pulse. This provides the best of both worlds—a fast current-mode feedback that doesn't require a high MIPS processor, and the ability to set a maximum duty cycle for current limiting.

To implement a digital current-mode system, begin by determining the PWM frequency and maximum duty cycle required by the SMPS design. These parameters configure the PWM's counter section. Next, scale the reference DAC output to the expected maximum range of the current-feedback signal. This provides the highest resolution when controlling the PWM duty cycle.

Finally, design the proportional integrator differentiator (PID) software code. The code takes the voltage feedback from the ADC, compares it to the internal digital reference, filters it appropriately for stability, and then outputs the desired current setting to the DAC that generates the comparator reference (Fig. 7, again).

To handle current-mode stability problems with duty cycles greater than 50%, the PID software sets the required current level so scaling the DAC value becomes a trivial task. This makes implementing slope compensation in the digital world easier than in the analog world, because it only requires software control. An analog solution requires a ramp generator synchronized to the PWM pulse as well as a summing junction. (In the latter, the ramp adds to the current feedback.)

The result of this process is a simple, current-mode SMPS that uses cost-effective, 30-MIPS DSCs to accomplish what a 1- to 2-BIPS processor does the hard way. This DSC only needs to calculate a new desired current level before the start of the next pulse. As a result, the DSC should have enough free time to accomplish other tasks, such as communications, system monitoring, and deterministic functions that include soft-start/ power-up sequencing and handling fault detection and recovery.

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