Electronic Design

Digital ICs> Reprogrammable Logic

FPGAs Absorb More System Logic

Gains made in density and performance are pushing FPGAs into an ever more competitive position with custom-designed ASICs. On top of that, they're virtually going head-to-head with "platform" and "structured" ASICs. The demand for FPGAs remains strong as designers craft systems that both meet the latest standards and are adaptable if the standards should change.

Unlike the fixed designs of an ASIC, FPGAs offer design flexibility not possible with custom circuits. At the same time, though, the high-density FPGAs are physically much larger, making them less cost-effective as a volume solution. The fast turnaround time and almost zero nonrecurring engineering charges offset the higher cost of the silicon for small to moderate production needs.

FPGAs are actually moving in two directions. On one path, they're pushing toward higher gate counts to compete with the high-gate-count large ASICs that sell for hundreds to thousands of dollars each. On the other path, the FPGA vendors are developing lower-cost, low- to moderate-density FPGAs that can compete with commodity ASICs selling in the range of $10 to $20 apiece.

To help lower volume production costs, Altera produced a mask-configurable equivalent device called HardCopy. It can lower component costs in the moderate production volume range, typically 10 to 50 kunits. Actel also plans to release low-cost moderate-capacity versions of its ProASIC flash-based FPGAs that will sell for about $5 in large quantities.

The high-density FPGAs available today from Actel Corp., Altera Corp., and Xilinx Inc. offer designers from 1 million to 3 million system gates and well over 400 I/O pads. In some cases, the number of I/O pads desired will determine chip size. That's because in a traditional chip design, the pads are laid out on the chip's perimeter. However, for both improved performance and more flexibility, future chips will distribute the I/O connections across the surface so that flip-chip manufacturing techniques can be applied. Distributing the I/O across the surface reduces overall chip area and signal I/O delays, improving chip performance. It will also allow FPGA suppliers to create next-generation chips with a thousand or more I/O connections, gate capacities of 10 million gates, and embedded memories totaling over 1 Mbit.

Many larger FPGAs incorporate system resources such as blocks of RAM, high-speed phase-locked loops (PLLs), processor cores (ARM922T for the Altera Excalibur, PowerPC for the Xilinx Virtex II families), and high-speed serial I/O (low-voltage differential signaling or multigigabit serializer/deserializer blocks). When these resources are integrated, the chips closely resemble the ASIC structured arrays with one key difference: Instead of metallization to define the circuit configuration, the FPGAs use RAM-based logic cells. In the case of the HardCopy array from Altera, there's a one-to-one match to the concept of the structured array.

Predefined silicon functions are also on the rise. But the challenge faced by FPGA suppliers (and by the structured ASIC vendors) is to avoid over-specialization by defining functions that would be of broad interest. Designers at Xilinx think they may have an answer with a modular chip architecture that makes it possible to craft optimized FPGA chips for different application domains. In development is the ASMBL (application-specific modular block) architecture, which combines strips of general-purpose programmable logic and strips of dedicated logic functions that provide support for a range of applications within an industry "domain."

QuickLogic's designers developed a very resource-rich chip called QuickMIPS. It combines a MIPS 32-bit processor core, a 10/100 Ethernet interface, 75 kgates of on-time configurable logic, and other resources. Another chip on the drawing boards combines the company's antifuse FPGA with the PACT parallel DSP compute array.

In addition to dedicated intellectual-property (IP) resources, the name of the game in FPGAs is soft IP. There are soft processor cores, such as the NIOS 16/32-bit processor offered by Altera or an 8051 core available from Actel. Soft IP also includes varied specialty functions to handle network interfaces, encryption/decryption, and so on. Deals are being inked left and right by the FPGA suppliers to bolster their design libraries. This will help shorten the design turnaround time by providing more of the building blocks needed by system designers.


  • FLASH-BASED FPGAs will increase their gate capacities from current 1-Mgate levels to capacities of close to 3 Mgates as Actel migrates to the next-generation flash process. Samples are expected in the second quarter.
  • THE FIRST SAMPLES OF SRAM-BASED FPGAs based on Xilinx's novel application-specific modular block architecture should appear toward the end of the year. The company expects the family to include devices with as many as 1 billion transistors on the largest family members.
  • BY LATE 2004, expect both Altera and Xilinx to have engineering prototypes of FPGAs packing close to 10 million system gates. These FPGAs, based on the latest 90-nm process technologies, will employ as many as 10 levels of metal interconnections to provide the necessary routing for all RAM-based configuration options.
  • PRODUCTION QUANTITIES of the recent Eclipse II low-power, low- to medium-density FPGAs should be available from QuickLogic in the first and second quarter. The family includes devices ranging from 47k to 320k system gates and exhibits standby currents as low as 50 µA.
  • EXPECT MOST FPGA SUPPLIERS to jump on the PCI Express bandwagon, offering either hard or soft cores to implement the high-speed serial version of the PCI bus.
  • A 400-MHz DOUBLE-DATA-RATE memory controller interface will be available from Altera in the first quarter. The interface has been qualified with Micron 400-MHz memory modules and runs on the Stratix and Stratix GX FPGAs.
  • DESIGNERS AT XILINX have started work on defining a 10-Gbit/s point-to-point short-distance interface. The company expects to have a final draft of the interface definition available by mid-2004, with samples of the interface possibly in early 2005.
  • EXPECT TO SEE FLIP-CHIP-PACKAGED FPGAs coming from Xilinx and other FPGA suppliers. The use of flip-chip technology allows FPGA suppliers to achieve higher performance because the electrical paths from the chip to the pc board are shorter. In addition, I/O connections can be distributed across the chip's surface, reducing the wiring complexity in trying to route a signal to the edge of the chip.
  • LOOK FOR DESIGN SECURITY to get more attention from FPGA suppliers. The value of the IP used within the FPGAs is rapidly increasing, so FPGA suppliers must find ways to protect that IP from being copied by someone that can capture the bit stream on RAM-based design. Antifuse and flash-based FPGAs have less of an issue, since the configuration data is stored on the same chip and can't easily be extracted.
  • MILITARY AND SPACE-CAPABLE versions of high-density flash- and antifuse-based FPGAs will arrive from Actel in the first quarter of this year. The ProASIC arrays and the latest antifuse arrays offer two to four times the gate capacity of the previous space/military-qualified FPGAs offered by the company.
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