Electronic Design

FIFO Simulates Large Shift Register

In some cases, when dealing with long bit streams that require large storage capabilities, a FIFO memory can be used to handle the data without needing any additional logic for reading, writing, and organizing. The diagram in Figure 1 demonstrates how to organize a FIFO to implement such a large shift-register.

To overcome the original 9-bit data organization of the FIFO, the D0 input is used as the bit-stream input. It’s written into the memory by clocking the WRITE strobe. After the first 2 kbits of data are stored, the FIFO_FULL (FF) output will go low. At this point, only the first shift register (i.e., the LSB bit position) of the memory is filled with significant data. Now, for each new bit written into the FIFO, one bit is output from Q0 and simultaneously written into D1, which is the input the next shift register.

This operation is repeated until the entire memory is filled (Q1 into D2, Q2 into D3, etc.), as shown in Figure 1. This can be accomplished by using only one OR gate.

After the FIFO_FULL flag goes low for the first time, the single OR-gate causes a read operation to occur simultaneously with each write operation. Thus, for one bit loaded in, one bit read out and written into the next shift register during the same operation cycle (Fig.2). When all the 9*2k data bits are stored, the FIFO is completely full and can be interpreted as a 9-tapped, 18-kbit shift-register (Fig. 3). The size of this shift register can be changed by simply choosing a FIFO with the appropriate size.

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