Electronic Design

Flash-Based Microcontrollers Are Rapidly Taking Charge

While ROMs still rule in today’s embedded systems, flash-based microcontrollers win the majority of new designs.

Flash memory-based microcontrollers have changed the landscape for embedded applications. Programming speeds and access times have improved. Flash reliability is no longer a concern in all but the most demanding environments. Flash memory-based microcontrollers have effectively knocked off one-time programming (OTP) technology and are even beating out ROM-based solutions in some security-conscious environments.

Mark Buccini, MSP430 product line marketing manager for Texas Instruments, indicates that while ROM-based microcontrollers account for about half the current shipments, flash-based microcontrollers have garnered more than three quarters of new design wins.

Flash memory technology has proven especially cost-effective for designs that require smaller quantities. David Lamar, senior marketing manager for microcontroller products at NEC Electronics, says flash-based microcontrollers are often used in an initial production run where ROM may eventually be used for cost savings. This gets products to market quickly and provides flexibility in terms of updates while products gain the benefit of field testing.

Flash memory technology's nonvolatile nature makes it the perfect complement for microcontrollers. The ability to reprogram a flash memory enables field updates and storage of relatively static information, like configuration settings.

Flash-based microcontrollers are expected to dominate the world of embedded applications for at least a few years to come. While contenders are under development, like Motorola's MRAM, they're only in the experimental and testing stages (see "MRAM: A Replacement For Flash?" p. 54).

Because microcontroller environments are very demanding in terms of reliability, price, performance, and power consumption, general adoption of these new technologies will take years. Flash-based microcontrollers are typically available in the same form factor with the same pinouts as OTP- and ROM-based solutions. This has allowed flash-based microcontrollers to be used interchangeably. If new technology is implemented in the same fashion and doesn't have special power or pinout requirements, then the speed of acceptance will be improved significantly.

If employing flash memory were simply a matter of including a block of silicon, there would not be such a variety of products. The figure shows how flash-based microcontrollers may employ a number of different techniques to improve performance, reliability, and programming time, among other things. Flash-based microcontrollers usually include at least one of these techniques. A number of these are typically found on high-performance or very low-power microcontroller products.

Low Power: ROMs consume very little power and are nonvolatile to boot. But flash-microcontroller designers keep pushing down the power re-quirements, making power less of an issue when choosing a microcontroller. Geoff Lees, director of marketing for Philips Semiconductor, says the LPC900 microcontroller draws as little as 1 µA in power-down mode and just 2 to 10 mA at full speed, depending on the peripherals used and the processor clock speed. This low-power operation is based upon a design that minimizes flash power requirements without resorting to additional hardware, such as instruction caches.

Microchip's nanowatt technology addresses lower-power operation by applying multiple design techniques. These range from multiple power-management modes to support for a number of selectable clock sources. Slowing down the processor reduces system power consumption, including power necessary for flash-memory access.

Microchip's PEEC (PMOS Electrically Erasable Cell) flash technology provides low-power operation and long- term data retention (on the order of 40 years). To improve manufacturability, the PEEC cell utilizes a merged cell with a Fowler Nordheim tunneling region instead of a defined tunnel dielectric window. The single transistor architecture performs more like a two-transistor flash architecture in terms of reliability.

Cyan Technology takes a different approach to minimizing overall system power requirements. Cyan's eCog employs an SRAM instruction-caching system. SRAM consumes less power than flash and has a faster access time. The cache reduces the number of flash memory accesses with its associated increase in power consumption. Typically, there's a charge pump drain of a few milliamps when flash memory is accessed. Caching is employed by a number of systems, usually to increase processor execution speed.

The eCog's cache allows programmers to lock code in the SRAM cache. Normally, a cache will toss out old code to make space for new code. This can be a problem for interrupt response. If the main application prevents the interrupt code from being cached, then interrupt response time and power consumption will increase. Locking the interrupt code in the SRAM makes power and speed usage predictable.

Combine this with a downshift to a lower clock speed, and the eCog consumes only 10 µA. This approach works very well for battery-operated, radio-based mobile devices where a device is typically waiting for a message. When the eCog detects incoming information, it can switch to high-speed mode, unlock the cache, and receive and process the data. This lets the eCog support even high-powered devices that idle the 802.11 interface for long periods.

High Performance: Flash memory provides the nonvolatality and reprogrammability that designers demand, but fast access and cycle times are not a big selling point. Flash memory designers continue to wring out as much performance as possible, although it's unlikely that flash memory will ever challenge SRAM, the other memory found in every microcontroller, in terms of speed.

One way to deliver code to the processor core faster is to use a flash memory that is wider than the processor's instructions. Widths of 8, 16, and 32 bits are standard for flash memory arrays in microcontrollers. But Philips Semiconductor's new 32/16-bit microcontroller family, based on the 32-bit RISC ARM processors, uses a two-transistor cell because it's more rugged and requires a lower voltage than a single-transistor approach. Additionally, it has a minimum retention time of 10 years and memory cells that are protected from such disturbances as programming adjacent cells. The microcontrollers will employ a 128-bit wide flash memory bus that's four times wider than the RISC instructions.

Cygnal Integrated Products also gives its 25-MHz flash memory a boost of four times, enabling the 8051 processor core to run at 100 MHz. The company uses a 32-bit wide flash memory to supply the 8-bit instruction stream to the processor, but this is only a start. A 4-byte prefetch buffer provides sufficient buffering to allow sequential access to the flash memory at the 100-MHz rate.

Moreover, Cygnal includes a 64-entry instruction cache to keep things moving when the application execution varies from a sequential flow. The 32-bit entries feed the prefetch buffer, allowing the processor to run at full speed as long as code is accessed sequentially, or the code is contained in the instruction cache.

Ubicom's 120-MIPS (millions of instructions/s) IP2202 needs to run at top speed in many communications environments, which is why it packs two banks of SRAM. One bank can be used for program memory if an application explicitly moves code from flash memory to SRAM. Applications can run directly from flash memory, but only with corresponding hits in performance and power. The trick for programmers is to keep frequently executed code in SRAM. This isn't too difficult given the availability of 16 kbytes of SRAM for the task. The split between code and data in this SRAM was arbitrarily decided upon to allow developers to trade off faster execution speed for more data space.

Making It Secure: While lower power and high speed are the usual considerations associated with flash-based microcontroller designs, security is an often overlooked feature. A number of different security issues come into play with flash microcontrollers. Protecting the code from snoopers is a concern to many whose intellectual property is frequently the main distinguishing factor in many products based on flash microcontrollers. Another issue is the prevention of improper read or write accesses. Restriction of read access enables data to be hidden or encrypted while the prevention of accidental writes protects an application from overwriting itself.

With regard to securing application code, Eugene Feng, business director of application specific product group for Silicon Storage Technology (SST), says that flash memory is more sensitive to physical dissection than ROM. So while a determined pirate could crack open a chip and access a ROM directly, accessing a flash memory in this way will usually corrupt its contents.

SST's FlashFlex51 family of 8051-compatible microcontrollers uses the company's SuperFlash CMOS technology. Its SoftLock feature prevents flash memory updates. The feature is en-abled by setting an address in flash memory for the routine allowed to perform the updates. Knowing the address for this routine, how it works, and where it's located will be necessary to update the flash memory.

SST's secure programming takes advantage of SST's in-application programming (IAP). IAP has a deterministic write time and can employ a dual- block configuration, which allows writes to occur in one block while another block accesses program code.

Switching blocks could be a problem for interrupts that implement an interrupt vector in flash memory. SST addresses this possibility by allowing interrupts to be redirected to a different flash-memory block.

Because SST's sector size is just 64 bytes, it requires fine-grain control. But the small sector size also eliminates the need to update much larger blocks (64 kbytes for many other systems).

Another feature of the SuperFlash technology, soft partition support, lets data be stored in flash memory that's not used for program memory. A DMA engine and mailbox register interface enables the use of flash memory as data storage without significantly affecting program execution. The interface moves data in the background instead of requiring an application to wait for the completion of flash memory writes.

Whatever the embedded-system design needs—low power, high performance, or security—flash memory technologies exist to deliver the features. As a result, flash memory-based microcontrollers will be the primary choice for embedded-system designs for many years to come.

Need More Information?
Cyan Technology Inc.
(781) 246-4646

Cygnal Integrated Products
(512) 327-7088

Microchip Inc.
(480) 792-7200

Motorola Inc.
(954) 267-5000

NEC Electronics Inc.
(408) 588-6000

Philips Semiconductor Inc.
(800) 234-7381

Silicon Storage Technologies Inc.
(408) 735-9110

Texas Instruments Inc.
(800) 336-5236

Ubicom Inc.
(650) 210-1500

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