Toshiba Corp. announced this week that it has made advancements in its development of a gate stack and interlayer with high carrier mobility that can be applied to metal-insulator-semiconductor field-effect transistors (MISFETs) in future generations of LSIs. The ultra-thin, high-k, Ge gate stack and strontium germanide (SrGex) interlayer can provide the high carrier mobility needed for application in MISFETs at the 16-nm node and beyond.
Current MISFETs use silicon for the channel, but the physical limitations of silicon do not allow it to obtain the drive current needed for future scaled-down devices. Germanium (Ge) has higher carrier mobility characteristics, but significant technical challenges exist in implementing germanium in LSIs. Development of gate stack structures for Ge-MISFETs is one of the challenges. High hole mobility has been achieved by using germanium dioxide (GeO2) in the gate stack insulating layer, but its low dielectric constant makes it challenging to reduce the equivalent oxide thickness (EOT) to 0.5 nm, which is required for the 16-nm node.
Toshiba developed a technology that overcomes the twin challenges of fabricating a thin gate stack while maintaining high hole mobility. The solution is obtained by inserting SrGex, a compound of strontium (Sr) and germanium, as an interlayer between the high-k insulating layer and the germanium channel. Germanium is first subjected to heat surface treatment in an ultra-high vacuum, and a layer of strontium of up to ten atoms thick is deposited on the surface of the germanium. This is followed by a lanthanum aluminate (LaAlO3) high-k film. Finally, the gate stack is annealed in a nitrogen atmosphere. The SrGex layer is formed between the high-k film and the germanium channel during these processes.
The new technology realizes peak hole mobility of 481 cm2/Volt second (Vsec), a record high value for high-k Ge p-MISFETs. This value is over three times than that obtained without the SrGex interlayer, and over twice the universal mobility that can be realized with silicon (based on comparison with the same gate field).
Toshiba also confirmed that a gate stack structure with EOT as thin as 1 nm was successfully formed, and that the increase in EOT by inserting the SrGex interlayer was only 0.2 nm at the most. This suggests the possibility of further EOT scaling to 0.5 nm, either by reducing thickness of an overlaying high-k layer or adopting a high-k layer with a higher dielectric constant.
See associated photo.