Electronic Design

High-Density CPLDs Deliver More Gates At Half The Cost

By revamping the internal architecture of its complex programmable logic devices (CPLDs), Altera developed a CPLD family that offers four times the gate count of its predecessor. The MAX II family also delivers those gates at half the cost and only one-tenth the power of its MAX devices. To do so, Altera switched from the traditional macrocell structure previous CPLDs used to a lookup-table approach similar to that used in FPGAs. (For a look at the chip and lookup-table architectures, go online to Drill Deeper 7675.)

Rather than use SRAM cells alone to hold the configuration data, the MAX II's on-chip nonvolatile flash configuration memory configures the lookup tables upon power-up. This gives the devices an "instant on" capability, as opposed to the tens or hundreds of milliseconds SRAM-based FPGAs need to load the pattern from an off-chip configuration memory.

The flash memory is reconfigurable while the device is operating as well. Real-time updates to the configuration can be done without interrupting the existing function. As a result, system operation can be altered on the fly.

Along with configuration flash, the MAX IIs include an 8-kbit user flash memory. This memory block will eliminate small serial or parallel EEPROMs that are typically used to hold system configuration or "housekeeping" data. Ultimately, system cost could drop by $0.50 to $2.00.

When fabricated in a 180-nm process, the resulting chips are one-fourth the size of competing devices using similar design rules. So, Altera can sell the chips for half the price of previous MAX devices at comparable gate counts.

To keep the chip small, the company uses a double staggered pad ring around the perimeter. This permits almost twice the number of I/O pads (up to 272 user I/Os) as the single pad ring without increasing the perimeter. Or, it permits the same number of pads in a smaller perimeter.

Four initial models are on tap. The EPM240, 570, 1270, and 2210 offer the equivalent of 192, 440, 980, and 1700 CPLD macrocells, respectively. The corner-to-corner worst-case propagation delay for the chips is 4.5, 5.5, 6.0, and 6.5 ns, respectively, and the best case delay for all devices is just 3.6 ns. With an expected mid-year release, the EPM1270 will be the first device sampled.

Altera's recent Quartus II version 4.0 design tools support the chips. Designers can download a no-cost version of the Quartus II Web-edition tools at www.altera.com/q2webedition.

In lots of 100,000, the EPM240, 570, 1270, and 2210 are expected to cost $2.00, $3.10, $5.60, and $9.50 in 2005.

Altera Corp.

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