Electronic Design

IEDM Charts The Course For Future-Generation Semiconductor Devices

The International Electron Devices Meeting (IEDM) is very well known for laying the groundwork for future semiconductor devices and associated fabrication processes. This year's event, held last week in San Francisco, was no different. Several sessions shed new light on recent progress and future challenges for a variety of semiconductor technologies, primarily driven by exploding wireless and wireline communications applications.

Lawrence E. Carson of the University of California's Center for Wireless Communications discussed developments in the high-speed analog and mixed-signal arena. Carson's invited paper highlighted the increasing role of silicon/silicon-germanium (Si/SiGe) biCMOS in future RF and analog sections of emerging communications systems, as designers battle to improve the dynamic range of CMOS circuits scaled below 0.15-µm gate lengths.

According to Carson's paper, #32.1, the high transconductance per current and high fT at low collector voltages makes the bipolar device in a biCMOS process an ideal candidate for low-power, high-performance applications. But the underlying CMOS must provide the state-of-the-art performance to get the optimum price performance from this merged process. So the key issue is the added cost of a heterojunction bipolar transistor (HBT). The paper added that CMOS and biCMOS both will continue to advance and encroach upon the gallium-arsenide (GaAs) turf below 5 GHz.

Meanwhile, GaAs HBTs have found a clear niche as power amplifiers. High linearity, gain, and breakdown voltage, in addition to single-supply operation, continue to make GaAs HBTs an attractive technology for power-amplifier applications. Carson indicated that silicon HBT power amplifiers also are advancing to compete with GaAs HBTs in some applications. He said MEMS is a promising technology for addressing key issues in optical-switching and low-loss mi-crowave switching circuits used in communications systems as well. Since these devices can be fabricated with traditional silicon VLSI techniques, the improvement over conventional ap-proaches can be substantial. But several material issues need to be resolved before MEMS can find widespread acceptance, Carson concluded.

Driven by the need for ultra-high-speed transistors at low power consumption for future optical and wireless communication systems, Hitachi's Central Research Laboratory and Device Development Center have jointly developed a 0.2-µm (200-nm) self-aligned selective-epitaxial-growth SiGe HBT/CMOS technology. Using this new biCMOS process, Hitachi's re-searchers have demonstrated an fMAX of 180 GHz for a SiGe HBT with an ECL-gate delay of only 6.7 ps.

Since this process employs a silicon-on-insulator (SOI) on a high-resistivity substrate, as well as multilevel interconnects, it enables the fabrication of high-quality passive elements on the same chip. The passive elements include a metal-insulator-metal (MIM) capacitor, high-precision resistors, a varactor diode, and a high-Q octagonal spiral inductor. And based on 10,000 parallel-connected HBTs, yields for an HBT are about 99.9997%. Hitachi's findings were presented in paper #32.2.

Scientists from Infineon Technologies detailed an npn SiGe HBT with an fMAX of 128 GHz in paper #32.3. Implementing these speedier bipolar transistors, the 88-GHz frequency divider with a 1.9-dB low-noise amplifier (LNA) operates at 12 GHz. Stanford University researchers also disclosed the first results of a pnp HBT made on a silicon/silicon-carbon/silicon (Si/SiC/Si) epitaxial process in paper #32.4.

Recent advances in SiGe HBTs were explored in session 7. Scientists from Lucent Technologies reported on the integration of SiGe bipolar, CMOS, and various passives for cost-effective applications in paper #7.1. NEC's researchers discussed thermal tradeoff and germanium profiling techniques to improve the performance of SiGe HBTs in a 0.18-µm RF biCMOS process without compromising CMOS characteristics in paper #7.2.

As system-level integration is driving the integration of passives on-chip, papers in session 7 investigated the challenges of integrating thin-film MIM capacitors and resistors in RF CMOS and biCMOS processes using copper interconnects. MIM capacitors and thin-film resistors are replacing traditional doped silicon and polysilicon approaches to lower the parasitic capacitance between the passive element and the silicon substrate. In paper #7.3, Motorola re-searchers revealed techniques that let designers place these passive elements between two successive damascene copper metal layers. Aside from minimal parasitic impact, this approach improves linearity, lowers the temperature coefficient and noise, and provides better matching of the passive components.

Besides bandwidth, speed, low power, and low cost, emerging wireless applications are demanding higher levels of RF functions on silicon substrates that can hold devices like single-chip transceivers. This has motivated the Delft University of Technology's Laboratory of Electronic Components to develop a novel micromachining post-process module. The lab's post-process fabrication technique is applied to the wafer's backside with precise alignment to the frontside. Using this method, researchers have developed micromachined microwave structures and transmission lines with improved mechanical stability. The results were presented in paper #20.2.

Researchers also revealed progress in RF power amplifiers using a compound semiconductor material like gallium nitride (GaN). In paper #16.1, engineers from Cree Lighting demonstrated a 50-W AlGaN/GaN high-electron-mobility transistor (HEMT) amplifier that's over six times more powerful than traditional GaAs-based amplifiers of the same size. Using 100- to 150-µm wide and 0.5- to 0.6-µm long gates, the researchers achieved a power density of 9 W/mm. Scaling it to an 8-mm width, the GaN-based power HEMT achieves a record power output of 51 W at 6 GHz.

To demonstrate the new power capability of a GaN-based HEMT, the Cree developers built a single-stage Class AB amplifier. For optimum thermal performance, the amplifier was flip-chip bonded to an aluminum-nitride (AlN) substrate, on which MIM capacitors, metal resistors, and air-bridge interconnects were fabricated to complete the amplifier circuit. According to this paper, the pulsed power measurement was performed using a 0.5-µs pulse width and a 5% duty cycle.

Several papers in session 16 investigated novel thermal oxidation and passivation processes for GaN devices. By using a newly developed thermal-oxidation technique, researchers at Matsushita Electronics Corp. have realized extremely high device isolation and a high-breakdown voltage for an AlGaN/GaN heterojunction FET (HFET). In a joint development, scientists at DaimlerChrysler AG and Korea's Advanced Institute of Science and Technology have together shown the impact of surface passivation on AlGaN/GaN HEMT devices. Using silicon-nitride (SiN) passivation, these scientists have improved output power, power-added efficiency (PAE), and gate-drain breakdown voltage.

Instability-related material quality and trapping effects are crucial to the reproducibility of GaN-based mi-crowave power FETs. Consequently, better understanding is required to eliminate these problems during fabrication. To analyze these issues in more detail, researchers from the University of Padova and the University of Parma have jointly studied the trapping phenomena in GaN MESFETs. The electron trapping effect significantly degrades power in these devices, especially in the mi-crowave region. And, it's a serious problem. Complete results were presented in paper #16.5.

The final paper in the session, #16.6, focused on a very low-distortion 230-W GaAs-based HFET with a field-modulating plate (see the figure). Intended for cellular basestation applications, the FP-HFET based power amplifier uses four chips in a push-pull configuration to deliver 230 V (53.6 dBm) at 2.1 GHz with an 11-dB linear gain and 42% PAE. The performance at 2.1 GHz was demonstrated using a 22-V supply with a drain bias current of 3 A. Also, the new power amplifier offers a low adjacent-channel-leakage power ratio of −35 dB, according to the developers at NEC's System Devices and Fundamental Research Laboratory.

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