Electronic Design

IP Pulls It All Together

Just as in the ASIC world, cell libraries and logic-synthesis tools help designers quickly turn designs completed with high-level design languages into circuits. But many functions don't easily or efficiently convert from HDL code to logic.

To achieve the desired performance, a lot of logic and/or layout hand-tweaking may be necessary. Or if you don't have the expertise to design the block or are under time-to-market constraints, an expedient approach is to license a block of intellectual property (IP) that performs the desired function.

FPGA vendors have developed many popular complex functions or worked with various third-party suppliers to qualify their functions for use on the FPGA fabrics. These functions can range from CPU cores that span the 8- to 32-bit realms, USB controllers, double-data-rate (DDR) DRAM controllers, MPEG compression/decompression engines, Ethernet media-access controllers, and many other blocks.

Depending on the performance desired, these blocks often come as either a soft core or a ?firm? core. A soft core allows the synthesis and place-and-route software to implement the logic. As a result, it may not offer the best performance in the system. A firm core is pre-synthesized and pre-placed and routed. Then, it's just ?dropped? into the final FPGA configuration.

By pre-synthesizing and pre-routing the block, the provider can guarantee a specific level of performance. This approach ensures consistent performance for speed-critical functions such as PCI X and PCI Express interfaces, DDR DRAM controllers, and so on.

Designers can achieve maximum performance by prefabricating the core in the FPGA's silicon. These cores, often called ?hard? cores, resemble the blocks of memory or MACs already available in some FPGAs. A few chips in the Xilinx Virtex II Pro and Virtex 4 families come with embedded PowerPC processors.

Such cores often deliver operating speeds 1.5 times to twice that of the soft or firm cores. Other companies integrate DRAM controllers and Ethernet media-access controllers to ensure they provide the desired performance.

In a bit of a turnabout, rather than instantiate a dedicated core to provide a specific task, designers at Stretch Inc. embedded a block of configurable logic in the datapath of a Tensilica CPU. The instruction-set extension fabric in the Stretch S5000 series processors can be configured to supply custom instructions to accelerate time-critical instructions.

This significantly improves performance over a core with the standard instruction set. Such an alternative requires a good set of software tools to help define the instruction extensions and compiler changes to fully integrate the new instructions.

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