Mobile multimedia is a hot market, and myriad vendors have new offerings designed to amaze and dazzle while sipping lightly from the battery trough. Such is the case with four product families from ARM, MIPS, ZiiLabs, and VIA Technologies.
The ARM Cortex-A5 and MIPS M14K and M14Kc lines are new architectures that the customers of these vendors will be using to build new chips. Meanwhile, ZiiLabs and VIA Technologies are offering new chips using their own designs.
Arm’s Cortex-A5 comes in one- to four-core versions (Fig. 1). The basic cores are built around a single-issue eight-stage pipeline with advanced dynamic branch prediction. The four-core version typically achieves a 95% hit rate using branch target and global history buffers. Limited dual issue of direct branches provides even better performance. The architecture is designed to deliver up to 1.5 DMIPS/MHz.
The memory subsystem has only a single-cycle load-use penalty for access to the L1 cache. The AMBA AXI memory system is up to three times faster than its predecessor in the ARM1176JZ-S. The system also supports multiple outstanding transactions with the external memory to fully utilize the CPU.
The cores use the ARMv7 architecture with optimized L1 caches. This includes support for Thumb-2 and the Jazelle DBX and Jazelle RCT Java-acceleration technology. The cores also are optimized for Just In Time (JIT) and Dynamic Adaptive Compilation (DAC). They can reduce the memory footprint by a factor of three as well.
ARM’s TrustZone technology helps with secure transaction handling. The floating-point and Neon signal-processing units are optional. Neon extensions accelerate multimedia codecs such as H.264 and MP3.
MIPS builds on its popular M4K line with the M14K and M14Kc lines. The M14Kc, which is the more advanced of the pair, includes full memory-management unit (MMU) support and memory protection (Fig. 2). Each line has a five-stage pipeline that delivers up to 1.5 DMIPS/MHz.
The chips can execute MIPS32 or the new microMIPS code, which is a compression instruction set architecture (ISA) that maintains 98% of MIPS32 performance with a 35% reduction in code size. It includes 15 new 32-bit and 39 new 16-bit instructions. Code can be recompiled to take advantage of the new ISA.
Another new feature, interrupt chaining, is designed to reduce interrupt latency and overhead when multiple interrupts are pending. Transitioning to a new interrupt handler while one is active takes only seven cycles. This approach only adds 21 cycles of overhead in this instance compared to 30 cycles on the M4K.
The cores are similar, but the M14K targets the Cortex-M3 arena. It provides memory protection and a 2- by 128-bit prefetch that is essentially a small cache. The M14Kc adds real caches and an MMU, allowing it to run operating systems like Linux. It targets higher-end platforms like ARM’s ARM926.
The ZiiLabs ZMS-08 multimedia processor is built around a 1-GHz Cortex A-8 processor with 256 kbytes of L2 cache and a 64-cell parallel processing array. The Cortex A-8 supports ARM’s Neon, TrustZone, Thumb-2, and Jazelle Java instruction sets. The parallel processing array is used for multimedia encode and decode chores.
The processing array is divided into blocks of eight cores, providing eight processing blocks. Each block can run its own code, allowing incremental improvement by using more than one block. Also, each is independent, so one can handle video while another handles audio. The array can handle simultaneous encode and decode of 720p H.264 streams as well as display 1080p at 40 Mbits/s.
Also, the array is fully programmable. ZiiLabs delivers a range of codecs and drivers, including OpenGL ES 2.0 and hardware-accelerated image compositing. Drivers for Adobe Flash and Xtreme Fidelity X-Fi audio are included. The Xtreme Fidelity X-Fi audio driver handles CMSS-3D sound, echo cancellation, noise suppression, and multimicrophone beam forming, enabling high-end operation in telephone and video phone environments.
The ZMS-08 has the usual complement of peripheral interfaces, including five UARTS and three SD/CE-ATA interfaces. A pair of high-speed USB 2.0 ports supports On-The-Go (OTG). The external memory interface can support single-data rate (SDR), double-data rate (DDR), or DDR2 devices.
The ZMS-08 video support is impressive. It supports HDMI and has a TV encoder that supports other interfaces such as component video. Four independent video units can drive 24-bit LCDs.
Several development platforms are available for the ZMS-08, including the self-contained Zii EGG (Fig. 3), a small-outline dual-inline memory module (SODIMM), and a development board based on the SODIMM with all I/O available for interfacing.
The VIA Technologies 2-GHz Nano 3000 delivers 20% more performance using 20% less power than its predecessor. This x86-compatible processor targets HD media devices with the ability to deliver 1080p content via hardware acceleration. Its ability to run Windows 7 enables developers to target lightweight notebooks and all-in-one desktop PCs.
This 64-bit superscalar incarnation supports virtualization as well as SSE4 multimedia single-instruction multiple-data (SIMD) instructions. The VIA Padlock Security Engine delivers hardware encryption support. The family has an 800-MHz V4 bus and draws as little as 500 mW when idling. It uses only 100 mW when running the core at 1.4 GHz.