Over 1 billion transistors on a logic chip. Over 16 billion on the latest flash memories. Logic clock speeds of 3 GHz and higher. Such numbers are the fruits of advances in lithography, metallization, and other aspects of semiconductor manufacturing.
Yet the power dissipated by so many circuits switching so rapidly has finally forced CPU and system-on-a-chip (SoC) designers to rethink their approach. Just improving the architecture and increasing the clock speed doesn’t cut it anymore.
One major trend in 2006 will involve CPU designers moving to multicore approaches. By integrating two or more cores on one chip, designers can reduce power while getting more work done with a reduced clock rate. Intel and AMD now offer dualcore CPUs, Sun has an eight-core UltraSPARC, and many more multicore solutions are in the works. Intel, for example, has over a dozen multicore processors in development.
But altering the chip architecture won’t be enough to reduce power and still boost performance. In process technology, 90-nm processes are hitting their stride. Toward the end of 2006, 65-nm processes should come online, with mass production targeted for 2007. Yet finer features won’t be enough either. Shrinking features create increased leakage currents, which take a bigger bite out of the power budget.
To help quench that appetite, as well as enhance performance, several companies have combined 90-nm processes with silicon-oninsulator (SOI) technology to trim device leakage. AMD, Chartered Semiconductor, Freescale, and IBM are producing CPUs and other devices using SOI processes.
SOI won’t be enough, though, as dimensions drop to 65 nm and below. In the meantime, new approaches such as the use of strained silicon can improve transistor performance without moving to 65 nm and smaller features.
STRAINED SILICON Without changing design rules, strained silicon can improve circuit performance by 30%. The straining is accomplished by adding several process steps that deposit special materials (typically a nitride) around the gate region to compress the silicon (p-channel FETs) or create a tensile strain (n-channel FETs). The n-channel devices have germanium atoms in the silicon lattice of the source and drain regions (see the figure). For the p-channel devices, a stress-memory effect can be created in the source and drain regions.
Single-strain and dual-strain strained-lattice structures can be implemented on devices fabricated in bulk silicon or in SOI wafers. Recently published results at the International Electron Devices Meeting in Washington, D.C., highlighted the efforts of a collaboration between AMD and IBM using a dual-strain approach on SOI. Designers achieved a 30% overall improvement in switching speed over non-strained structures.
Intel also uses strained silicon in some of its high-performance processors. For future processes, Intel will explore the use of fin-FETs. In these 3D transistor structures, control elements surround the gate on three sides. By surrounding the gate, the control signal can better turn the gate on or off, switching the gate faster and reducing gate