An increasing proportion of today's silicon products is destined for applications in the consumer marketplace. At the same time, more consumer products are becoming "untethered," relying on battery power and putting tougher constraints on chip designers to reduce the power consumption.
Recent financial results from a leading foundry showed a rapid jump in revenue proportion from 0.13-µm technology (11% in Q1 to 17% in Q2). Mainstream designs are starting to use 0.13-µm geometry. Leakage problems in these 0.13-µm standard logic processes, however, are challenging designers. Compared to 0.18 µm, individual transistor leakage increases by more than an order of magnitude at 0.13 µm. In addition, 0.13-µm chips average more than twice as many transistors. The net result is an increase in chip leakage of greater than 20 times. For many applications, this can dramatically limit the standby battery life. Although the use of high-threshold-voltage transistors can reduce the severity of this increase, it significantly reduces performance.
With memory representing the majority of the die area (and an even higher proportion of the transistor count) on today's SoCs, designers are increasingly looking at different memory technologies to help in the battle against leakage. So what are the memory innovations that will help overcome leakage in the latest generations of process geometry? First, it is important to understand that for traditional embedded memory, most leakage is caused by the fact that each six-transistor SRAM bit cell contains four leakage paths across the power supply. Thus, 10 Mbits of memory will represent more than 40 million transistors worth of leakage across the power supply. Although some process techniques can be used to attempt to reduce this leakage at the expense of performance and/or manufacturing cost, not much can be easily done to improve the situation due to the inherent power-supply leakage paths in the six-transistor static RAM bit-cell design.
In contrast, dynamic bit-cell designs, such as those used by DRAM or MoSys' 1T-SRAM memory technology, are not connected permanently across the power rails and, therefore, avoid these dc circuit leakage paths. Such bit cells do require periodic refresh to replace charge lost on the bit-cell storage node. But good architecture, circuit design, and layout techniques can reduce the average current required to refresh the bit cell to substantially less than the leakage current occurring in a six-transistor bit cell in the same process. How is this so? Refresh is required to replace charge that has mainly been lost through a single transistor (rather than four). In addition, because this transistor is not in the active cross-coupled configuration of the transistors in the static bit cell, it can be biased to suppress almost all of the subthreshold leakage. In fact, in a typical "generic" 0.13-µm logic process, the refresh current can be as little as one-fifth of the leakage generated by the static six-transistor design.
This counterintuitive result may surprise many who remember the early datasheets of CMOS devices in the 1980s that touted the benefit: "Fully static design consumes no dc current." Twenty years later, dynamic memory boasts much lower standby current than these fully static designs! Interestingly, design style may have to come full circle as the underlying transistor characteristics have changed so dramatically over those 20 years. So what about the next 10 years? I predict that embedded memory will be dominated by dynamic bit-cell designs, not just because of superior power consumption, but also due to the significantly smaller die area.
This may also be a precursor to a future direction for logic design in applications where low power consumption is important. Although memory represents the majority of leakage, applying dynamic circuit design techniques to logic may further help in the battle to reduce standby power requirements. Who knows? Maybe, just like clothes, the design styles of 30 years ago will again come back into fashion!