Electronic Design

Logic Architecture Cuts Mask And Silicon Costs

Based on an improved logic architecture, the ASAP (Area, Speed and Power) family of high-speed metal programmable cells and high-density standard cells significantly reduces mask and silicon costs. Members of this family also cut the price and power consumption of the overall chip while improving its performance. The devices target the consumer, communications and networking, graphics, and handheld markets.

The patented ASAP routing and cell architecture optimize routability and minimize power consumption for deep-submicron applications. The underlying architecture provides the same performance as competitive standard cells, with shorter cell sizes. It's been silicon-proven on a range of process geometries (from 0.35 to 0.13 µm) and is compatible with existing tools and design methodologies. Products built on this technology typically increase logic block area usage by over 20%. Thanks to the use of shorter wires, smaller transistors, and wider metal spacing, they provide significant increases in pin accessibility and power routing. The ASAP devices are being launched on TSMC's 0.13-µm (130-nm) logic process.

The metal programmable cells significantly reduce mask costs for 130- and 90-nm process geometries. Thus, the metal programmable cells overcome a key barrier (high mask costs) to low- and medium-volume system-on-a-chip (SoC) implementation without causing any performance degradation. They provide area and performance characteristics comparable to conventional standard cells without the penalty of all-layer costs.

Since designers can reconfigure the chip by changing only two to four metal layers, the metal programmable cells reduce mask costs by up to 50%. In the ASAP standard cells, the new architecture heightens pin accessibility and eliminates cell placement blockage from the power grid. The standard cells deliver a 20% minimum savings in logic block area over conventional standard cell architectures.

Licensing of the ASAP high-speed metal programmable cells starts at $50,000 per design. The ASAP high-density standard cells carry a minimum licensing fee of $25,000 per design for fabless customers.

Virage Logic, (877) 360-6690; www.viragelogic.com.

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