Staking claim to the highest macrocell count of any complex programmable logic device (CPLD)—1080 macrocells—the ispLSI 8000V line offers up to 1440 internal registers and up to 360 I/O registers. Known as the SuperBIG family of in-system PLDs, these chips combine very high densities with 125-MHz operating speeds and 8.5-ns pin-to-pin logic delays.
The ispLSI 8000Vs have an embedded three-state bus that can be configured as either twelve 9-bit buses or in combinations up to a single 108-bit bus. Built-in bus-arbitration logic prevents internal bus contention. This embedded bus also can be used as an internal bus or as an extension of an external three-state bus.
The CPLDs' architecture consists of general-purpose macrocells grouped into five, seven, or nine Big Fast Megablocks (BFMs). Each BFM consists of six generic logic blocks that are 20 macrocells wide and have 44 inputs each. All the blocks are interconnected via a global routing pool (GRP), which acts like a programmable silicon backplane that adds a delay of just 2 ns for any route. A second-generation product-term sharing array supports up to 28 product terms per macrocell output.
Three models are initially available. The largest has 360 I/O pads and 1080 macrocells, while the smaller devices have 840 and 600 macrocells. All are 5-V tolerant, but they operate from a 3.3-V supply. I/O pins can be user-configured to operate with either 2.5- or 3.3-V I/O levels. Boundary-scan testing and in-system programming can be performed through the JTAG (IEEE 1149.1) test-access port included on all devices.
Samples of the SuperBIG CPLDs are immediately available. They come in 272- or 492-contact BGA packages. When housed in the 272-contact BGA package, the 600-, 840-, and 1080-macrocell chips sell for $41, $52, and $65 each respectively in 1000-unit lots.
Lattice Semiconductor Corp., 5555 N.E. Moore Ct., Hillsboro, OR 97124; (503) 268-8000; www.latticesemi.com.