About every two years, chip memory doubles?or even quadruples. Often, DRAMs set that pace. Of late, though, nonvolatile flash NAND memories are creating the benchmark for capacity.
This year, we'll see several 8-Gbit devices from various vendors. Also on tap are 16-Gbit NAND memory chips from Samsung Semiconductor. To achieve its record-setting density, Samsung developed a novel 3D cell structure and employed features as small as 50 nm to fabricate 16.4 billion transistors on-chip.
Designers at many companies are hard at work improving NAND flash-memory density to meet portable storage demands. You can thank the consumer market for this growing demand, too. Portable music players, digital still cameras, and solid-state video cameras all need larger memories to hold more tunes, capture more pictures, or play longer videos.
Many new technologies will debut at next month's IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco. Toshiba and SanDisk, for example, will present what they claim as the smallest 8-Gbit multilevel NAND flash memory. Based on 56-nm design features, the chip has a 99-mm2 area and a 10-Mbyte/s programming throughput.
While multilevel cell structures can double memory capacity, they aren't as reliable as single-bit/cell designs. As a result, NAND flash designers incorporate some level of error checking and correction (ECC). To ensure this reliability in single-bit/cell structures, STMicroelectronics and Hynix Semiconductor developed a 4-Gbit NAND flash chip with embedded 5-bit BCH ECC. The ECC scheme can correct up to five errors over a flexible data field of 1 to 2102 bytes.
Saifun Semiconductors and Macronix teamed up to produce a 4-bit/cell storage scheme based on Saifun's NROM technology. The key to this density breakthrough is a dual-phase programming algorithm that provides a fast and accurate threshold-voltage control.
NOR-based flash memories offer full random access rather than the word-serial access used by NAND-flash devices. While they're getting denser, they still remain several generations behind NAND flash chips in density. Last year, Spansion released the industry's first 512-Mbit NOR flash chip based on the 2-bit/cell Mirror-Bit technology and its 90-nm features. Intel Corp. released the 512-Mbit, 2-bit/cell StrataFlash device, also based on 90-nm process rules. Both companies plan to release 1-Gbit devices this year. Devices with larger capacities will appear in 2007.
As memory density increases, the cost per bit drops dramatically (see the figure). Since 2002, the cost for NAND flash has plummeted from just under $1/Mbyte to about $0.015/Mbyte. By 2009, it should fall to less than $0.01/Mbyte. The lower cost will open new applications. On top of that, it will displace the sub-10-Gbyte micro hard-disk drives now used in many portable music and video players.
Researchers are experimenting with phase-change, ferroelectric, and magnetoresisive technologies as alternatives to flash. Today's state-of-the-art in phase-change is a 256-Mbit device under development at Samsung. It employs 100-nm process rules.
Also on the slate for discussion at ISSCC is a 64-Mbit ferroelectric device developed at Toshiba using 130-nm design rules. A pair of 16-Mbit magnetoresistive devices will be revealed at the conference as well. Toshiba developed one using a combination of 130-nm rules for the CMOS layer and 240-nm rules for the magnetoresistive layer. The other, employing 180-nm rules, comes from a joint project between Infineon Technologies and Altis Semiconductor.
Though DRAM densities have temporarily leveled off at 1 Gbit, Elpida has taken the lead by starting to sample the industry's first 2-Gbit double-data-rate 2 (DDR2) device. While density growth at most of the other DRAM vendors has been idling, the variety of architectures to meet various system needs continues to expand. Standard synchronous DRAMs are now mostly relegated to legacy support, while double-data-rate 1 and 2 (DDR1 and DDR2) devices are in full production. In fact, DDR2 devices have hit 400 MHz (800 Mbits/s).
Volumes of DDR2 devices are starting to match volumes of DDR1 devices. Shortly, DDR2 will start displacing DDR1 in servers, desktop systems, and networking systems. Samples of next-generation DDR3 memories with data rates up to 1.3 Gbits/pin and 512-Mbit densities will be in customer hands this year, with limited production expected later this year.
Hynix Semiconductor is working on specialized high-performance graphics memories (GDDR). They will feature 2.5 Gbits/s per pin and 256-Mbit densities, nearly doubling currently available GDDR3 memories. Infineon has created a 512-Mbit device that will deliver 2 Gbits/s on each data pin. And Samsung's current GDDR3 memory, used in the Xbox 360, operates at 700 MHz and delivers data at 1.4 Gbits/s per pin.
Chips based on the XDR (extreme data rate) serial differential interface developed by Rambus Corp. will compete with the GDDR memories. Now offered by Toshiba and Samsung, these memories operate at clock rates of 2.4 to 4 Gbits/s per pin pair. Even faster speeds are due out next year.For the low-power market, specialized versions of the DDR1 DRAMs are now available. They will offer extended refresh capabilities and on-chip circuitry that will monitor temperature and other conditions. This circuitry will let the DRAMs dynamically adjust the refresh period to minimize power while ensuring data integrity.