Electronic Design

MIPS-Family 64-Bot CPUs Hit Gigahertz Clock Speeds

Taking two paths to deliver high-performance 64-bit MIPS-compatible processors, PMC-Sierra Inc. has extended its RM9000 series of 1-GHz highly-integrated processors. The RM9220 and 9224 contain dual processor cores, three 10/100/1000 Ethernet media-access controllers (MACs), a generic packet interface, and a 32-bit PCI or an 8-bit Hypertransport interface that runs at up to 600 MHz (DDR). Also included are 16-kbyte level 1 caches for instructions and data and a 256-kbyte unified level 2 cache with error-checking and correction. A 200-MHz double-data-rate (DDR) SDRAM controller provides a peak bandwidth of 25.6 Gbits/s. The RM9220 comes in a 672-contact flip-chip BGA package, while the RM9224 employs an 896-contact FCBGA package. The RM9224 uses the extra pins for a PCI interface. Prices start at $379 for the RM9220, with samples available in the fourth quarter.

In addition to the dual-processor chips, PMC has added a trio of single-core 64-bit CPUs to its RM7000 family—the RM7900, 7965, and 7935. Based on the RM9000 64-bit core, the chips run at a top speed of 900 MHz. The CPUs include a 256-kbyte level 2 cache with ECC. The processors are pin-compatible with CPUs in the RM5200 family, allowing straightforward system upgrades. The RM7900 and 7965 have 64-bit system buses, while the RM7935 employs a 32-bit bus to reduce cost and pin count. The difference between the RM7900 and 7965 is a level 3 cache interface on the RM7900 that can address up to 64 Mbytes. Housed in a 256-lead TBGA, the 900-MHz RM7965 costs $150 each in lots of 10,000 units.

PMC-Sierra Inc.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.