Electronic Design

Multiservice Processors Keep Data Secure

The MSP2100, packing an IPsec engine to accelerate secure communications, performs 128-, 192-, or 256-bit real-time encryption.

On-chip IPsec data-encryption acceleration for 128-, 192-, and 256-bit keys, along with seamless wireless support for 802.11a, b, and g, are the key ingredients in a second generation of multiservice processors developed by Brecis Communications Corp. Each chip—the MSP2100, 2007, and 2005—offers a different mix of resources to meet various system price and feature requirements. Targeted applications include wireless routers and other secure data networking systems.

The MSP2100 packs the most features: an IPsec engine with random number generator, a 32-bit PCI bus interface, a trio of 10/100-Mbit Ethernet media access controllers (MACs), a 16-kbyte scratchpad RAM, a 32-bit MIPS 4Km processor clocked at 170 MHz, a 133-MHz SDRAM memory controller, and additional interface support. The IPsec engine delivers at least five times the performance of the company's previous-generation MSP2000.

The MSP2100's architecture offers wire-speed performance thanks to the dedicated IPsec engine, the high-speed MIPS processor, and a 4.25-Gbit/s on-chip multiservice bus. The MSP2007 targets wireless routing and has a subset of the MSP2100's features: It lacks the IPsec accelerator and only has two 10/100-Mbit Ethernet MACs. Simpler Ethernet routers and firewalls combined with an Ethernet switch can look to the MSP2005. The 2005 is similar to the 2007, but it costs less because it eliminates the PCI interface, which isn't needed for low-cost routers.

In volume, prices for the MSP2005, 2007, and 2100 are under $10, $15, and $20, respectively. FastStart kits are also available with support for VxWorks, Linux, and custom operating systems.

Brecis Communications Corp.
(408) 437-9900 www.brecis.com

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