Electronic Design

Network Processor Core Employs Programmable State Machine

The STAR (Scalable Tile Architecture) packet and protocol processor core is a compact programmable networking processor. Based on a programmable state machine (PSM), the core contains a simple instruction set for packet and protocol processing.

According to the company, the STAR approach (see the figure) can support bandwidths from T1 to 2.5 Gbits/s per port for Ethernet or POS (packet-over-SONET), with support for up to 10 Gbits/s in the near future. The core contains an instruction set optimized for multiple networking protocols, such as IP-over-SONET, IPV4, IPV6, MPLS, ATM, and frame relay. With the company's SmartConnect feature, multiple STAR tiles can be connected together. This increases the number of ports and protocols that can be handled by a given piece of hardware.

Each STAR soft macro contains approximately 3500 ASIC gates. Since there is little die-size penalty in putting several cores on one chip, the company believes this is a very cost-effective way to deliver products with a very low cost per port. A STAR tile also can be programmed to handle support for virtual private networks, IP tunneling, layer 2/layer 3 address learning, and other quality-of-service features and functions. According to the company, this firmware approach will ultimately result in faster time-to-market as well as ease upgrades.

Additionally, each STAR contains a dynamically loadable code space that is initialized on system reset. Specific sequences of states are listed, which personalize each particular instance of the STAR.

With several STAR tiles on a chip, the programmable firmware increases the flexibility to change, debug, and upgrade a product anytime after the silicon is built. Other core features include 150-MHz speed in 0.25-µm technology, MIS (memory interface socket) interfaces with on-chip memory controller, and cyclic redundancy check (CRC) blocks to perform CRC for AAL5 and IP headers.

Synthesis scripts are provided with the core, which is a Verilog-based design. By combining STAR tiles with cores from its CoreNet networking library, the company says that designers can create products for the entire range of networking solutions. These would run the gamut from servers and switches to carrier backbones.

The STAR packet and protocol processor is available now. Contract pricing, product and reference design details, and engineering support may be obtained by contacting the company directly.

Stargate Solutions Inc., 2160 Lundy Ave., San Jose, CA 95131; (408) 954-8302; fax (408) 954-8303; Internet: www.stargateip.com

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