Electronic Design

Network Processor/Framer Combo Pursues Multiprotocol Termination

Headaches can ensue when dealing with the complex multiprotocol termination and interworking functions required to interconnect the existing access technologies to the converged intellectual-property/multiprotocol-label-switching (IP/MPLS) service provider networks. A remedy may be on the way, though, in the Mission Access chip set, an OC-12 network processor and an integrated HDLC controller/channelized framer. This cost-effective chip set from AMCC can become the catalyst to implement the network transitions closer to the access points where user traffic originates.

The Mission Access set can simultaneously migrate or tunnel services such as time-division multiplexing (TDM), Frame Relay (FR), asynchronous transfer mode (ATM), and Ethernet into a common MPLS network. It also can interoperate virtually any combination of these services in already deployed networks. This functionality eradicates complex network overlays and seriously reduces management costs and backhaul expenses for the T/E access infrastructure. The set consists of the Amur (S1215) framer and multiprotocol data-processing device and the nP3705 network processor and traffic manager.

The S1215 handles configurations ranging from STM-4/OC-12 (622 Mbits/s) to 32xT1/E1/J1. It implements all of the framing, overhead processing, timing control, and standards-compliant Sonet/synchronous-digital hierarchy to plesiochronous-digital hierarchy (DS3/ E3/DS1/E1/DS0) channelization and mapping functions. There's support for ATM, HDLC/PPP/FR, and Generic Framing Procedure (GFP) framing for up to 1024 channels ranging from 56 kbits/s to 155 Mbits/s. In addition, the Amur family handles flexible interfaces to terminate voice and TDM payloads.

Able to manage traffic data rates from 50-Mbit/s to 2-Gbit/s full-duplex packet/cell processing bandwidth, the nP3705 ultimately extends AMCC's nP5 architecture. Internally, the nP3705 integrates multiple network-optimized programmable coprocessors designed to deliver wire-speed performance while processing complex nested protocol stacks and mixed ATM/Packet payloads. A broad range of configurable interfaces is possible with the processor, including OIF SPI-4.2 and SPI-3 buses and ATM Forum Utopia Level 2, as well as Gigabit- and Fast-Ethernet ports with built-in media access controllers.

A modular application software suite including ATM Layer, Inverse Multiplexing over ATM, Frame Relay (FR), Multi-Link FR, Multi-Link Point-to-Point Protocol (PPP), MPLS, and Metro Ethernet VPN components supports the Mission Access chip set. The suite builds on an extensive software infrastructure, including a full integrated development environment. Sample quantities of the chip set will be available in the first half of 2005, with the S1215 selling for about $850 and the nP3705 costing between $350 and $700, depending on speed grade.


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