Flash memory, the dominant technology for nonvolatile storage, has constantly improved over the last 20 years, with still further enhancements expected over the next decade. But emerging nonvolatile technologies promise to deliver higher performance and greater endurance than flash memory. These new technologies—based on Ovonic, ferroelectric, and magnetic materials—offer different benefits, enabling designers to better match a technology to their application (see the table "Comparison of Non-Flash Technologies").
FLASH STILL SIZZLES
The extremely thin-oxide (ETOX) technology used by most suppliers of NOR- and NAND-based flash memory is moving into what Intel calls its eighth generation as feature dimensions shrink to 0.13 µm. Several companies have already developed next-generation 90-nm processes that will squeeze 2 Gbits of NAND-based storage onto one chip. Earlier this year, Samsung Semiconductor disclosed details of a single-bit/cell 2-Gbit chip that can run from a 1.8-V supply. It will offer a block erase time of 2 ms, a page program time of 300 ms, and a read access time of 25 ms for the first access and 50 ns per subsequent access during a burst cycle.
Competing with the thin-oxide structures, a thick-oxide memory cell developed by Silicon Storage Technology, dubbed SuperFlash, serves the moderate density flash requirements, currently up to 16 Mbits/chip and shortly moving to 32 and 64 Mbits. The cell's main advantages include a fast store time and simple manufacturing process that's very easy to integrate into the standard process flow for CMOS digital and mixed-signal products.
A multilevel-charge (MLC) storage scheme, developed by designers at Intel and now several other companies, doubles a memory array's storage capacity. The MLC scheme divides the stored charge in the cell into four levels. Then, using three comparators, it can determine the charge value of the charge and thus the level it matches. By assigning values of 00, 01, 10, and 11 to the four levels, the charge value will determine the bit representations.
Initially applied to NOR-style memories by Intel, suppliers such as M-Systems/Toshiba, Samsung, SanDisk, and Hitachi (now Renesas Technology) have applied their versions of the MLC approach to NAND-based (or AND-based) memory architectures. Hitachi recently demonstrated a 1-Gbit MLC AND-based flash memory that has a 10-Mbyte/s programming speed. To help keep the chip size under 95 mm2 when produced using 0.13-µm design rules, the company developed an assisted-gate AND-type memory structure and a very compact SRAM write buffer. The fast programming speed is possible thanks to a constant-charge-injection programming technique. This reduces the programming time by 20-fold versus conventional AND arrays.
Back to NOR-style memories, the MLC technology was most recently applied to create a 128-Mbit device fabricated with 0.13-µm design rules. The prototype chip from Intel actually contains 64 million cells squeezed into a chip area of 27.3 mm2. It can operate from a 1.8-V supply and performs read operations in just 55 ns. Subsequent burst-read operations can be done at 125 MHz, making this memory device the fastest flash memory to date. Commercial samples of the chip are available.
Intel won't stop at two bits per cell. Already, research is under way to determine if four bits per cell would be technically practical. That would require 16 charge levels to be defined in the memory cell, and those levels must remain stable over temperature and other system conditions. This might still be several years from commercialization.
Competing with the MLC technology is a nitride-oxide memory cell structure developed by Saifun Semiconductor. The NROM cell can also store two bits, effectively doubling the bit capacity of memories based on the cell. Advanced Micro Devices (AMD) and Fujitsu have collaborated with and invested in Saifun, and both are developing families of flash-memory devices based on what AMD calls the MirrorBit technology.
Rather than use different levels of charge to represent the bits, the MirrorBit scheme can independently store two full-margin charges, one on each end of the transistor gate in each storage cell (Fig. 1). Then, a sensing scheme can detect whether or not a charge is present on either end of the gate to read either bit, or both bits. AMD says that this approach is inherently more reliable than the MLC scheme because the full charge is used for each bit.
Also applied to NOR-architecture flash memories, the MirrorBit technology will let AMD manufacture chips with capacities ranging from 16 to 256 Mbits. As lithography features continue to shrink, the technology is expected to achieve densities of 1 Gbit per chip by late 2004. In contrast, Strataflash MLC devices from Intel are available in capacities of up to 128 Mbits, with 256-Mbit devices expected in late 2003.
Rather than double the bits per cell, designers at Matrix Semiconductor developed a write-once technology that stacks layers of memory cells one above the other. By building layers vertically, chip area remains the same. As a result, memory cost rises only slightly as storage capacity increases (see "Write-Once Has A Place," below).
By using the various flash technologies as a yardstick, a number of companies are creating extensions of, and simplifications to, the ETOX technology. They're also coming up with radically new technologies that promise denser and higher endurance nonvolatile storage.
One of the extensions to the flash storage cell involves the use of nanocrystal floating gates. Designers at Motorola created nanocrystal memory cells by forming a layer of 50-Å silicon dots, deposited on a 50-Å grid on top of the thin gate oxide layer. Another oxide layer is deposited on top of the nanocrystal layer, and then the polysilicon gate is formed on top of the oxide.
Due to the discontinuous nature of the charge storage layer, the material doesn't exhibit vulnerability to isolated defect paths in the underlying tunnel oxide. Thus, the tunnel oxide under the nanocrystal layer can be scaled down, reducing the voltage needed for program/erase operations—8 to 10 V, as opposed to the 12 to 15 V used for most floating-gate storage cells. The structure can also be used to implement storage cells that either use an MLC or MirrorBit-like approach to pack two bits in each cell.
Furthermore, memory cells based on the nanocrystal approach are smaller than most other floating-gate structures. The nanocrystal technology is also a relatively simple extension to standard CMOS processes, requiring just four additional mask steps. Consequently, it could lead to low-cost chips that combine logic and nonvolatile memory. Motorola's researchers anticipate that products could be sampled by 2005.
CHALLENGERS TO FLASH
Phase-change materials are the basis for a memory cell developed by Energy Conversion Devices Inc. and licensed exclusively to Ovonyx Inc. Intel and Ovonyx have set up a development project to create a storage chip that employs the Ovonyx unified memory, or OUM.
The OUM employs a cell based on thin-film phase-change materials—a ternary compound based on germanium antimony tellurium (GeSbTe), which is similar to the material used in CD-RW and DVD-RAM disks. Rather than use light, the cell employs electrical energy (current pulses) to heat microscopic resistors in the silicon substrate. In turn, the resistors convert the phase-change material from crystalline to amorphous, or vice versa (Fig. 2).
No exotic processing is required for the OUM structures, and they can be readily scaled. Additionally, they can be easily integrated into the process flow of standard logic circuits, allowing memory/logic products to be developed with minimal cost overhead. The material also exhibits high endurance—over 1013 write/erase cycles without failure. Therefore, the memories can operate much like a low-power nonvolatile RAM.
Moreover, the phase-change material can be programmed to intermediate resistance values, enabling multistate data storage like that used in MLC arrays. Another benefit of the technology is its inherent radiation tolerance. There's no memory SER because the storage element is the phase-change material, not the silicon. Neither are there any charge-loss failure mechanisms, although excessive temperatures could alter the material state. In addition, low-temperature processing can be used to deposit the phase-change material, eliminating any potential compromise of the P-channel transistors due to thermal effects.
Intel has developed a 4-Mbit test chip based on the OUM technology and 0.18-µm design rules. The chip runs from a 3.3-V supply and has demonstrated over 1012 set-reset cycles.
Another area being explored in nonvolatile memories is magnetic materials. For instance, under development at several companies are the ferroelectric RAM (FeRAM) and the magnetoresistive RAM (MRAM). These companies foresee significant use of these memories in portable and other system applications.
FeRAMs are mostly based on lead-zirconium-titanate (PZT) materials. Tiny PZT crystals, which retain a magnetic state when a voltage field is generated, form the capacitor. The polarization of the ferroelectric crystals shifts between two stable states depending on the direction of the field. Those polarization states are sensed as Ones or Zeros.
Toshiba Corp., in conjunction with Infineon Technologies, developed a 32-Mbit device with a read access time of 50 ns when operating from a 3-V supply. In another joint development, Texas Instruments and Ramtron International Corp. crafted a 4-Mbit ferroelectric memory that combines the nonvolatile storage array and a 4-Mbit SRAM on one chip. The end result is a nonvolatile RAM that can operate at sub-60-ns access times. Another TI project bore fruit in a 64-Mbit test structure that can be used as embedded FeRAM for next-generation system-on-a-chip (SoC) designs. The test chips were fabricated using a 0.13-µm copper-interconnect process that only required two additional mask steps to add the ferroelectric storage elements.
Both Fujitsu Laboratories and Samsung Semiconductors are also pursuing FeRAM technology, with Fujitsu demonstrating a 4-Mbit FeRAM structure suitable for embedding into SoC applications. The chip offers an access speed of 30 ns when operating from a 1.8-V supply. Memory-cell endurance is at least 1013 cycles, and the one-transistor/one-capacitor cell structure minimizes the chip area required for the entire array.
The Samsung device leverages a new manufacturing technique that eliminates the etch step to form the capacitor. That simplifies the processing and makes it easier to integrate the FeRAM technology into the standard CMOS process flow.
One of the newest nonvolatile technologies to tempt designers is the magnetoresistive RAM. It combines a magnetoresistive device with standard silicon structures to achieve a combination of features not available in any other memory technology. MRAMs are nonvolatile and can operate at low voltages. They also have unlimited read and write endurance, they can read and write data at high speeds, and they're radiation hard. Such devices could replace a number of other memory devices in a system, simplifying system design and lowering system cost.
The memory cell consists of thin layers of magnetic materials separated by a thin aluminum-oxide layer. These layers form a magnetic tunnel junction that leverages the quantum mechanical tunneling of spin-polarized electrons through a very thin insulator (Fig. 3). The spin direction causes either a parallel low resistance or an antiparallel high resistance. Those two states are interpreted as the logic Ones and Zeros.
Though many test chips have been described at various conferences, Motorola hopes to be the first company to commercially sample an MRAM. The company already demonstrated a 1-Mbit device with measured read and program cycle times of just 50 ns. The first commercial chip will offer a capacity of 4 Mbits. Motorola hopes to sample it to customers in late 2003.
However, there are some challenges to overcome. First, the MRAM technology is a little too power-hungry, so steps must be taken to reduce the active and standby power. Next, to ensure good manufacturing yields, the variation in the magnetic behavior (bit to bit) must be minimized. Finally, the design must be scalable so that smaller cell sizes can be implemented.
In experiments with MRAM technology, researchers at Samsung developed a 64-kbit MRAM test structure that can be fully integrated with their standard 0.24-µm CMOS process flow. The largest experimental MRAM unveiled thus far, though, is a 512-kbit array developed by NEC Corp. The memory array's crosspoint cell structure incorporates a novel cell selection scheme to better access individual cells in the crosspoint array.
The use of colossal magnetoresistive thin-film resistors lets Sharp Corp. implement what it terms a "nonvolatile resistance RAM" or RRAM. The resistive element consists of many thin layers of praseodymium calcium manganese oxide (PrCaMnO), which is formed on top of an electrode composed of yttrium barium carbon uranium oxide (YBaCUO) on top of lanthanum aluminum oxide (LaAlO). The cell offers a lower-power alternative to MRAMs, operates slightly faster, and has the potential to be used in multi-bit/cell storage applications.
Although some of these technologies—OUM, MRAM, polymer—still aren't ready for prime time, they provide a view into what will be possible over the next few years. The days are numbered where designers must force-fit a memory technology to an application.
|COMPARISON OF NON-FLASH TECHNOLOGIES|
|Fast read and write, 1012 cycles||Fast read and write, 1012 cycles||Fastest read and write, unlimited cycles|
|High current/power||Lowest current/power||High current/power|
|Nondestructive read||Destructive read||Nondestructive read|
|"Bolt-on" process||Special process||Special process|
|Smaller cell size||Larger cell size||Larger cell size|
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Advanced Micro Devices Inc.
Fujitsu Microelectronics Inc.
Matrix Semiconductor Inc.
Ramtron Semiconductor Corp.
Renesas Technology America Inc.
Saifun Semiconductor Ltd.
Samsung Electronics Co. Ltd.
Silicon Storage Technology Corp.
Texas Instruments Inc.