The tried-and-true axiom of "you don't get something for nothing" certainly can apply to the latest multilevel NAND flash chips. Though they dramatically increase the memory capacity in a given core die area, it's at the expense of more complicated peripheral circuitry.
Illustrated is a block of 2-bit-per-cell NAND flash circuitry that consists of single-transistor memory cells connected to one of 32 control gate lines (CG1-CG32) and one of 32 bit lines (BL0-BL32) (see the figure). Also shown are two select gate lines (SG1, SG2) and a common source line. During write programming, the threshold voltage of each memory-cell transistor is set to one of four controlled threshold voltage levels by charge injection onto its floating gate.
Data is read from all bit lines in parallel, one row at a time. To set up conditions for the read operation, the select gate lines and all unselected control gate lines are driven high. Then, in sequence, four different word-line drive voltages are applied to the selected control gate line. When the drive voltage is higher than the threshold voltage of the individual memory-cell transistor, the corresponding bit line draws current.
Compared to a normal 1-bit-per-cell memory in which one clock period is required to read one bit, the 2-bit-per-cell memory requires four clock periods to read two bits—one clock period for each of the four word-line drive voltages. Additional peripheral circuitry is required to generate the discrete voltages and timing, as well as to code-convert the more complicated output data stream from the bit lines. Comparable increased circuitry also is required to program the variable threshold voltages during the write operation.
On an example 1-bit-per-cell memory chip, the peripheral circuitry occupies about 28% of the active die area, with the memory-cell array taking up the remainder. On a comparable part from the same manufacturer, but using a 2-bit-per-cell design, the peripheral circuitry uses 35% of the die area. Hence, 2 bits per cell reduce chip size and therefore chip cost, but not by the twofold reduction one might originally expect.