Electronic Design

PCI Express 3.0 Nears The Station

The PCI-SIG is working on the final iteration (v0.9) of the PCI Express 3.0 specification that makes some major deviations from the 2.0 spec to attain twice the performance. The progression has been 2.5 Gtransfers/s to 5.0 Gtransfers/s to finally 8 Gtransfers/s for 3.0. This translates into 2, 4 and 8 Gbits/s/lane. The standard lane configurations remain x1, x2, x4, x8, x16 and x32.

To achieve this higher throughput, PCI-SIG has switched from the 8b/10b encoding to the more efficient 128b/130b encoding. It requires transmitter and now receiver equialization and implements a dynamic approach with signialling embedded in data transfers. PCI Express 3.0 employs a scrambling technique that utilizes a binary polynomial in a feedback topology. This introduces more DC wander in the 128b/130b encoding scheme compared to the 8b/10b employed by PCI Express 1.0 and 2.0. It guarantees a consistent transition density over large intervals but the received clock data recovery circuit must be able to handle deviations in the short term.

The new specification introduces a number of protocol extensions to improve performance. They range from data reuse hints to indicate that data should be placed in cache as well as main memory, dynamic power adjustment mechanisms, loose transaction ordering and atomic operations. I/O page faults are addressed as well as BAR resizing.

PCI Express 3.0 is backwards compatible with 2.0 and 1.0. Matching standards define the mechinical specifications including the familiar PC card sockets and Mini-PCI Express as well as ExpressCard form factors. Cabling standards address 1.0 and 2.0 implementations. It remains to be seen whether 3.0 will rise above the backplane to box-to-box cabling.

Pericom Semiconductor will be sampling a pair of low jitter PCIe 3.0-compliant clock generators (PI6C557-03B and PI6C557-05B) as well as PCIe 3.0 compatible switches (PI3PCIE3412).



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