A fractional-N frequency synthesizer—a device that generates frequencies
in steps which are fractions of the reference frequency (f_{i})—will
typically employ a microprocessor. Described here, however, is a fractional-N
phase-locked loop (PLL) that replaces the microprocessor with a less expensive
voltage-controlled amplifier and some supporting circuits. The loop is always
maintained in the locked condition by changing the voltage-controlled oscillator
frequency.

In the proposed scheme, the modulus control of the divide-by-N counter is
implemented using a pulse remover (Fig. 1).
The overflow (ovf) pulse causes the pulse-removing circuit to become active,
thus no input pulse is applied to the divide-by-N counter. The effect of removing
the pulse is the same as if the divide-by-N counter has a division ratio of
(N + 1) instead of N. To maintain the same frequency and desired phase relationship
at the two phase-comparator inputs, the VCO_{1} output frequency (initially
N × f_{i}) is forced to increase by the same amount as introduced
by the overflow. When the PLL system is in locked condition, the output frequency
of the divide-by-N counter is the same as that of the reference. Therefore,
the input frequency of the divide-by-N counter is N × f_{i}, and
hence the output frequency of the VCO_{1} (f_{out}) is Nf_{1}
plus the ovf frequency.

The phase-detector (PD) output modifies with the change in N or F (fractional
part) input. This in turn forces a change in the output frequency of the VCO_{1},
whereby the divide-by-N counter's frequency is the same as that of the reference.
Thereafter, the effect of the PD is to bring the phase difference between its
two inputs to the initial constant value.

The ovf frequency is generated in such a way that it's the required fraction
(F) of f_{i}. With each additional increment in the fraction F, the
average value of the DAC output increases proportionally. The voltage-controlled
amplifier is used to make the output voltage level correspond to f_{i}
so that the ovf frequency generated by the low-pass filter-VCO_{2} cascade
is the required fraction of f_{i}. The frequency-to-voltage converter
(frequency discriminator) followed by an LPF generates the voltage corresponding
to f_{i}, which acts as the control voltage for the voltage-controlled
amplifier.

The PLL chip, CD 4046, is used to implement this scheme. It contains two phase comparators (I and II). Comparator I can lock in harmonics, whereas comparator II locks in only the fundamental. Zero phase difference is required in implementing the scheme. That's where comparator II steps in, because it can maintain zero phase difference over the entire VCO range. Comparator II, which is an edge-controlled digital memory network, works only on the positive edges of the signal and the comparator input.

The voltage-controlled amplifier is implemented using a common-emitter amplifier with a FET as its collector resistance. The FET's gate-to-source voltage thus controls the collector resistance. The pulse-remover circuit (Fig. 2) is implemented using negative edge-triggered JK flipflops (7473) with reset and AND gates (7408). When clear (CLR) is low, Q1 and Q2 are low and Q3 is high. After removing the CLR pulse, Q1 toggles to high with the ovf's falling edge. Next Q2 toggles to high with the falling edge in the input. With Q2 being low, the output is disabled. The next falling edge in the input makes Q2 toggle to low, which in turn toggles Q3 to low. This resets all of the flip-flops back to the toggle mode. Therefore, Q2 remains low for one complete cycle of the input, resulting in the removal of a pulse from the output.

Consequently, this scheme offers a design that doesn't require voltage compensation (at the PD output) or a microprocessor accumulator (with appropriate software to linearize the required fraction input, which would give the correct increment in ovf frequency), as is required in most present-day designs.

Instead, a frequency-discriminator-voltage-controlled amplifier-VCO combination achieves the same objective, making it less complex and less expensive. Further cost reduction can be achieved by integrating this design in chip form.