Preaching To The Converted

ASIC conversion is key to implementing FPGA designs, says Vince Hopkin.

Any discussion of programmable logic must include the role of the FPGA and, in particular, how designers can get the best out of their FPGA designs during design, development and final manufacture.

FPGAs offer designers the flexibility to test a design in the application without incurring large NRE charges and allow design iterations to be performed using the same FPGA prototype device until the final working solution is attained. Furthermore, high-density FPGAs have changed the programmable logic market by allowing users to prototype their applications with higher-performance solutions without incurring large cost and time penalties. This is particularly valuable within diverse markets such as communications, computing, and medical equipment where time-to-market (TTM) and low development costs are critical to the overall success of the end product. FPGAs serve these industries well by helping customers expedite their application development.

However, while they are often invaluable during the development phase, it is in the move to mass production that the use of FPGAs can start to cause the OEM a headache, not least in the areas of power consumption, component size, and cost.

Due to their programmable nature, FPGAs use a great deal more power than an application-specific part designed to deliver identical functionality and performance levels. FPGA implementations will rarely use all of the logic and memory available, meaning that a large portion of transistors remain unused yet active. Not only is this a constant source of power drain on the completed design, but it also means that OEMs end up paying for functionality that the application simply doesn't need. The large amount of programmable logic and memory available on today's FPGAs also results in a large die size, while programmable interconnects across the FPGA represent a significant portion of the chip and are another constant source of power drain. In routing a design through an FPGA, there is no direct path between any two points – a lot of switches are needed to turn on a given path. Using a large number of switches for a given route is a third source of high power use, and this power drain increases exponentially as clock speed rises. Finally, FPGA designers cannot use programmable interconnects with clocks. This results in the need for a large clock network across the surface of the die, again using a great deal of power.

There is one other problem facing FPGA users, a problem that FPGA vendors are loath to admit. The technology employed by programmable logic vendors hasn't changed much in the last 20 years. As a result, the performance of programmable logic fabrics has just about (or may even already have) hit the limit; mainly due to exponentially increasing interconnect delay.

It is clear that FPGAs are great for prototyping and low-volume production, but the bottom line is that any relatively complex mid- to high-volume design, where power consumption, component cost and size are important issues, requires another solution for mass production. And this is where the latest structured ASIC technologies can deliver significant benefits.

A structured ASIC is programmed in the upper levels of the fabrication process for a specific logic function. Logic that is not used in the circuit design is not connected and, in many cases, can be powered down to conserve total power usage. ASIC memories that are embedded in structured ASICs as large blocks are faster and use less power than FPGA memories.

Routing is also optimised to the shortest path between two points on the circuit, further reducing the power used. Finally, multiple clocks can be used and the circuit timing optimised to find the balance between power and performance. Considering all of these power saving options, it is common for a structured ASIC design to use 20–50% less power than the same design implemented in an FPGA. Furthermore, for a structured ASIC to match the performance of an FPGA, an ASIC technology one process generation behind the FPGA can be used.

For example, if a design is implemented in an FPGA which uses a 1.5V 0.13mm technology, the structured ASIC replacement can be implemented in 0.18mm or 0.15mm technologies that will still match the timing of the FPGA. Implementing a design in a lower cost, more mature structured ASIC technology allows for drastically reduced engineering costs since mask costs are increasing at an almost logarithmic rate.

So how can OEMs retain the low cost, flexible development advantages of using FPGAs at the same time as using structured ASICs to deliver final product that addresses the cost, power and size priorities needed for final production? The answer lies with FPGA-to-ASIC conversion. Using an FPGA-to-ASIC conversion methodology, system designers can quickly get their system designed and into production using FPGA technology – including the latest high-end devices. Then, once the design is fully proven, the design can be quickly converted to a structured ASIC. The low NRE charges associated with a structured ASIC, coupled with the a much lower unit cost, make this strategy a powerful tool in achieving low overall costs and improving competitive advantage.

And what about ASIC conversion time? Clearly, the time taken to convert to an ASIC can be an issue if the conversion is handled as an afterthought. However, by choosing a conversion company that can advise on how FPGA implementation can be optimised for subsequent ASIC conversion – and that can offer the necessary IP to take an FPGA prototype and convert it to a structured ASIC – it is often possible to have ASICs ready as soon as FPGA-based product trials are complete.

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